\\NT-2\DATA\Kerner\Switched Ref PLL\Switched Reference PLL User Manual.doc

Copyright Ó February 11, 2000 -Thomas M. Kerner It is a violation of federal law to intercept, modify, or in any way alter or use this document without permission from the author. All rights reserved by the author.

Please forgive the brevity of this document as it was prepared quickly, as the entire SRPLL was an afterthought necessitated by unanticipated consequences between the development of the RF based synchronous clock, and problems to Beam Sync users when that clock was removed, or not available.

We are still taking data from the field to qualify the sensitivity of equipment. See appendix for some brief magnitude studies.

Notes on using the V102 input shift control register are in the OPERATION section of this document.

First it is important to understand what the Switched Reference PLL (SRPLL) does, so that its command and control is straightforward.

Purpose:

• The primary purpose of the SRPLL is to replace the lost 28 MHz RF clock and revolution tick which go flatline for a short time while a cogging reset occurs. 28 MHz to DC is a large frequency excursion which causes a discontinuity in receivers and errors occur. The SRPLL will fill these gaps or discontinuities with a steady known frequency reference (synthetic clock and synthetic rev tick) which is close to (indistinguishable from) the original RF clock and rev tick. After a cogging reset, the SRPLL will end the synthetic clock and revolution tick, and re-acquire the new phase RF clock and revolution tick. The RF phase will slew at the rate of the SRPLL time constant which is relatively slow, but constrained over a very small frequency range, to limit the frequency excursions experienced by PLL receivers to avoid loss of lock or other aberrant behavior. The revolution tick will just be resynchronized with the new one in a step fashion which will not affect PLL receivers. A constraint is placed on the new rev tick acquisition: If the new rev tick phase is sooner than the old, the pulse is chopped out or ignored until the next cycle. This ensures that any equipment that uses the rev tick pulse downstream will not receive two pulses too close together to cause other aberrant behavior. The result is; there will be one longer than normal gap for every cogging reset that results in an out-of-phase rev tick.

• The secondary purpose is to provide a synthetic clock and revolution tick for off-line operation. We now have a mechanism to run diagnostics and system tests during the times that the RF chassis is being powered down, repaired, maintained or replaced, and when there is no beam in the machine. Downstream systems may also be developed using this approach. This goal is achieved by having a simple and redundant synthetic clock and rev tick sources which do not have to be synchronous with beam.

• The third purpose is to provide a low jitter system clock to the beam synchronous system. There is a timing limitation in comparing the zero crossings from the 0 dBm 28 MHz sinewave delivered when sub nanosecond precision is desired. Jitter is further reduced when recovered by PLL, and transmitted differentially as LVPECL to the beam sync system receiver.

• No frequency dependent phase shift will be placed in this box to correct for phase lead and lag experienced between particles at various speeds and the delivered timing. This function is a DDS function and the frequency dependent phase correction required can be accomplished in that module. This negative phase correction factor is independent of ion species, it is a pure function of the RF frequency. In RHIC the phase lead and lag for any single ion will be no more than a single bucket anyway. This would have never been in SSC. Had RHIC been designed with more buckets, then there would be a problem that must be addressed in this manner. The concept is simple, for any RF frequency, adjust the phase of the RF clock linearly and over a range of several cycles, to compensate for lead or lag at any one point of the machine, and all points of the machine will follow suit perfectly. So it is theoretically possible to do this in the phase accumulator of the DDS. The calibration should be straightforward, and since the sweep rate is small, the adjustment may be made incrementally with each frequency bump. If phase adjustment exceeds bucket boundaries, the revtick bucket 1 pulse must also be phased to allow being clocked in on the same rising edge of the rf clock.

• In order to prevent phase and frequency transients from affecting down stream devices when the reference is switched in and out requires that the SRPLL first finds zero phase relationship and then switches. This introduces a small delay, which is easily anticipated and handled by the controls system programming. If the two frequencies were identical it would never switch. If the two frequencies were different by 1 Hz it would take up to 1 second to switch. If the two frequencies were different by 1000 Hz it would switch in under 1 ms. It is inadvisable to switch greater frequency spreads than this, because the down stream G-Link components will not track them without loosing lock. So there is a trade off between fast switching times (large delta f) and not frequency shocking the downstream systems (small delta f).
• Some Downstream Beam Synchronous components are "touchy" to modest frequency or phase changes. An example is the narrow bandwidth circuitry used in communications PLLs in the PHENIX experiments.
• Low jitter is the primary goal of this system, all else can be compensated from that. PHENIX requires less than 1 ns of long term drift, and 25 picosecond jitter performance. Jitter is the driving factor because all Beam Sync timing is derived, adjusted and tuned from recovered beam sync carrier clock edges. The precision of the recovered clock edges limits system performance.
• A pair of rev ticks too close together has also caused some beamsync related problems on the beam position monitors which use the revolution tick to control processor executions. If the calculation time is longer than the two resynchronized revolution ticks, a crash resulted. These systems have been desensitized but the rev tick generator in the SRPLL will solve the problem for all downstream devices in just one location.
• Should the phase need to be adjusted on the beam sync system to correct for variations between the fixed propagation delay of the fiber optic distribution system, and the variable time of flight of ions or polarized protons in the rings, it is best handled at the synchro synthesizer in one location rather than at all locations around the rings. This is accomplished by changing the ion species independent, linear frequency dependent, phase delay in small increments. Then apply this to the RF clock going to the Beam Synch system.
• Galvanic isolation via transformer coupling will be provided on all inputs and outputs due to the low noise floor requirement in the PLL circuitry. Reference clocks use transformer coupled differential balanced LVPECL line receivers for lowest jitter RF clock transmission and reception. Digital inputs such as start and end reference inputs and rev tick input will have hysteresis receivers, and be transformer coupled to avoid noise.
• Inputs must be ESD insensitive
• RF shielding should be exceptional to keep out radiated and conductive (EMI & RFI) noise influences from the sensitive PLL circuitry, reducing system jitter.
• Power connections bypassed to grounded RF enclosure to minimize conducted noise.
• Reference mode can be controlled and observed through existing control system and observed on SRPLL indicators.
• Internal references are put into stand by mode when not in use to suppress crosstalk and noise induced jitter and minimize power consumption which also reduces temperatures in a non-ventilated enclosure. Normally one crystal runs at a time. Two crystals will run simultaneously immediately after shifting in a new reference selection, you must then wait 10 ms before sending a start reference pulse. After the start reference pulse is sent there is a zero phase match delay before the output is switched. This 10 ms stabilization time should be enforced programmatically. If the same reference is used, meaning that a new reference frequency has not been selected by shifting, then the 10ms stabilization time is not necessary. The start pulse may be administered immediately. The output then will switch upon zero phase match which is phase and frequency dependent. The deselected reference remains active on the output until the zero phase switch occurs. The 10ms overlap is necessary to prevent interruptions and instabilities in the reference frequency sources throughout the switching process when a new internal reference is selected. The power-up default is always the internal XTAL 1 clock with the first internal reference, XTAL 1 selected. Event setup and V102 programming must allow for these delays.
• Please note that the phase match feature is designed to work between REFERENCE MODE and RF MODE only, (not between references) there will be no output frequency change when switching between references without first switching to RF MODE and then switching back to REFERENCE MODE. (assuming all inputs are active) Whatever the last valid XTAL selection was, will become active when switching from RF MODE to REFERENCE MODE. When changing references, You must first stop the Reference (STOP = switch to RF MODE), and then start the new reference (START = switch to REFERENCE MODE). This makes sense. Back to back reference clock selections will not change the SRPLL output. The SRPLL is designed not to switch into a dead clock. If the RF clock should be missing, then the SRPLL will stay in REFERENCE MODE indefinitely. Should the RF clock fail, then the SRPLL will not be able to switch to the REFERENCE MODE.[ To avoid a functional impasse, the phase match logic may be overridden by executing the same command the second time. For example when in RF MODE and the RF clock has failed, commanding a switch to XTAL 1 twice will force it to do so without consulting the phase comparator. You need only use this feature when the RF clock has failed.] A direct change of reference clocks will not take effect until first STOP is issued and then START. For example; if you are already in Reference mode and then you issue a new XTAL setting followed by a START, the output of the SRPLL will not switch to the new Reference until a STOP and START are issued. This operation requires two phase matches to complete. This is necessary because there is no practical way to phase match any of the References to any other reference. So you must go back to the RF input first. Normal operation requires this anyway. It is expected that the new Reference will only be selected when the SRPLL is in RF mode.

• Although the concept of switching seems trivial, there has rarely been a necessary requirement to do it with the utmost accuracy and precision. RHIC and PHENIX have stressed this concern of accuracy and precision to the state of the art. The extreme precision in time and accuracy in space is a requirement. The conceptual handling of switching between various references and the swept RF clock to avoid phase transients on the beamsync links requires the implementation of a totally new structure, so as not to pass the problem on to another. The transients must be eliminated by zero phase comparison prior to being placed at the input of the PLL. The "frequency" adjustment will be transient in nature, but will be fully within the control loop parameters of the PLL. The design approach uses a zero phase zero and a zero phase one comparator. The implementation of this concept in hardware is not straight forward because the zero phase comparison must be highly accurate (in this application under 1 ns) which is not easily achieved in today's hardware, especially on such short notice, poverty budget, and with no tools to measure or quantify the results. I had to try all things by trial and error until the result was obtained. This was the hardest way to work, but the only way possible here. The aforementioned tools are all readily available, but beyond the reach of this department. Never-the-less, the importance of getting RHIC up and running should take precedence. Somehow these simple tools must work for us. The necessary tools have been placed into a document for management to winnow down. But I hear today that we should attain a scope and a signal communications analyzer within about 5 years.

• We cannot switch automatically to the REF clock should we detect an RF clock cycle slip. This is because we do not know what RF frequency we were operating at. We could be at injection, acceleration or storage. It is expected that before any discontinuities occur in the RF clock (by program control) that we will get the proper early warning event decoded by the V102 to switch the SRPLL. If we are not warned, we will expect that whatever beam was in the machine has been dumped. Power fault is not considered because these systems are on UPS. It is also assumed that the ion species injection and storage frequencies will be programmed into the proper reference crystals. These references will be selected depending on whether the RF was at injection or storage and what ion species was in the machine. All exotic ion frequencies must be set on the DDS before they are needed. Normally the RF clock will ramp down on its own. But if someone hits a reset from storage frequency, then we must use the DDS to ramp us down to avoid any false codes.
• If RF clock should be unexpectedly interrupted or disconnected, the SRPLL will lose lock. If the signal is zero, then the input will oscillate at 200 MHz. If the signal is very slow, then the SRPLL will adjust down to its lowest frequency around 15MHz and jump around.
• When the above happens any downstream PLLs will also loose lock. At any time the system may be put into REFERENCE mode and ignore the RF clock input. This is necessary if the input is temporarily disconnected to indicate an input failure has occurred as there is no way to run intelligently without input.
• There is a small delay period when switching between internal references. This is to allow the crystal oscillator to power-up and stabilize when its OE is turned on. This requires only about 200 microseconds. When switching between references, there is a zero phase comparison delay which is inversely proportional to the frequency difference. A 1Hz difference would take up to 1 second to switch. A 10Hz difference would take up to 100 mS to switch. A 1kHz difference would take up to a millisecond to switch. Etc.
• Had we switched to REFERENCE mode automatically and stayed there, it would be very hard to decipher (diagnose) afterwards why the beam sync system is not locked to the RF clock, as no readback status is available from the SRPLL. Previously, a seek routine caused the PLL to seek around about a 15kHz frequency ramp between the predetermined minimum and maximum frequency window programmed into the PLL. On further examination, it is obvious that if locked to the RF clock, an RF interruption will cause the jitter sensitive experiments to crash anyway. But to successfully kick out beam in the beam dump, I must allow the reference to switch in automatically, not by manual control as management has mandated. Tough on management. I have to do the right thing at the right time. If they want to know if RF is still running in the SRPLL they will have to ask it and the RF group's synchro synthesizer source clock too. So I will allow switching to a live reference (the last active selected reference), this is necessary. To switch out of a dead (interrupted) input to a live one requires some fancy footwork not to jump out too soon nor too late. Too soon and you jump out on noise, too late and the loop filter/integrator will drift too far( this is fast for low noise low jitter systems). Not to switch into a dead reference is much easier. We can even wait for a dead reference to become live before we switch. Upon interruption a transient will happen anyway throwing PHENIX off-line. If these rules are followed carefully, then there is no need to override the SRPLL with the controller:

1. By design, never allow the SRPLL to switch from a live source into a dead reference.
2. By design, always phase match before switching (live to live) (an asynchronous operation and indeterminate wait with bounds always results based upon sound existing principles, 0f 0 or 0f 1).
3. By design, allow switching between live RF, and any live REF, AND between any live RF and any other live RF using transient free zero phase matching.
4. Let all unused REFs sleep to reduce noise and power. Awaken unused REF a short while before use to gain stability, usually 10ms before they can be switched-in. The only time that two REFs are running simultaneously is during this 10ms period, and then switch after a zero phase match, putting the "old" oscillator to sleep on this switch. This allows us old slow folks to accomplish things at a speed that we could never attain before. Kind of like a little operator in a can that moves faster than we can see, but brings us the results everytime. Then by multiple simulations we can get the error out. Just like a computer only different, because computers can't do this. (comment redacted).
5. Automatically switch out of a dead input to the "other" last selected live input without phase match. Then return with phase match if the "other" dead input is resurrected. Normally, REFs are always available, and at least one is always running. There can be up to 8 fixed frequency XTAL REFs (rings for the chin rubbers), and a single DDS REF which can be swept and phase modulated as necessary, and the RF input. Most of the time there will be three live sources: RF, DDS, and one of eight XTALs. Your choice of fixed XTAL frequencies can be mounted internally which will represent the ion species at baseline injection. A dynamic frequency can be supplied by the DDS, but watch out that most commercial DDS have a large jitter on the output, a limitation of this kind of design. And then there is the RF source, which if it could be dependable without error then none of this would be necessary. But we all know that the RF must go through cogging resets because of the nature of the separate rings and LINAC. Until now. Now it is possible to do all this on the fly, faster, on command, but with an asynchronous deterministic delay that is kept within bounds, without a hiccup. Just like a three ring circus juggler.
6. This approach should help solve all data correlation problems as well, and increase operational stability and up-time that is ever so expensive, while keeping radiation as low as reasonably achievable through excellence in design, precision, attention to detail, nothing missing, nothing broken whole system solutions in a can. Well at least we hope so.
7. All elements of this design are scalable. They can be made to operate at arbitrary frequency, precision and accuracy by design. The only limit to phase accuracy and frequency are the design efficiency and speed grade of the components. Which means this bodes well for the future.

• "REFERENCE ON" - This green LED indicator on the front panel will illuminate when the SRPLL is in REFERENCE mode. Green is informational. No action is required.

• "DDS > PLL" - This green LED indicator on the front panel will illuminate when the frequency on the DDS (or selected internal XTAL clock oscillator) input is greater than the frequency put out by the SRPLL. This will happen mainly when in RF input mode and the RF input is less than the selected reference. The selected reference may be the DDS or one of the eight internal clock oscillators. Green is informational. No action is required.

• "PLL > DDS" - This green LED indicator on the front panel will illuminate when the frequency of the PLL is greater than the frequency of the selected reference, when in RF input mode. This provides a visual indicator if the selected reference has a greater frequency than the RF input. (During an acceleration ramp or storage it is expected that the PLL will be at a higher frequency than the internal reference. One of the internal references must be set up and running before the time that it is needed during the cogging reset.) Green is informational. No action is required.

• "SYNC ERROR" - This red LED indicator will illuminate whenever there is an error in the revolution tick pulse. This error should only happen when the cogging reset is performed (when the RF clock source is switched to a reference clock source, and vice versa). It should never happen at any other time. This indicator will illuminate if the rev tick is disconnected. This indicator will also illuminate if the rev tick is shifting with respect to the RF clock. This indicator will illuminate whenever there is a single dropout or phase change between the RF clock and the REV TICK input. Specifically, if there is more or less than 360 RF clocks per REV TICK. It is pulse stretched for visibility. Red is bad. Action is required.

• "NO LOCK" - This red LED indicator will illuminate whenever the PLL has any trouble locking to the input RF clock. A simple test is to go to REFERENCE mode and this LED should go out when the PLL locks to the reference. Normally indicates that there is a RF clock problem, no input, out of frequency range, excessive jitter, poor signal strength etc. If the REFERENCE mode has been set to use the external DDS input, this input is probably bad or missing. Try switching to an internal reference XTAL clock oscillator. A visual test to see which of the internal XTAL clock oscillators is loaded and working is to observe the NO LOCK LED stays off while that reference is selected. Red is bad. Action is required. This indicator should never flicker or appear dim. It should be completely off.

• Eight internal clock references are available at any one time. If there are 8 or fewer commonly used reference frequencies required, they can be accommodated if the controls group is given in advance an exact frequency to within 50 ppm. Up to 8 clock references with custom frequencies can be added to the SRPLL. Revisions may be made by swapping out clock references. There is a limit on how many replacements may be made because these devices must be added and removed by a solder process at this time. Use the DDS reference input for more rapid frequency substitutions and flexibility. The DDS jitter is typically too high for PHENIX use, but it may be reduced enough by the SRPLL to be useful. Only one of the internal clock references will run at a time to suppress noise, this requires the other devices are all placed in standby mode, and must be turned on no less than 10ms before stable output is realized.

There are two signals that are generated by the RF group's Synchro Synthesizer board which undergoes the cogging reset:

The RF synchronous clock is supplied by the RF group's Synchro Synthesizer. This clock is transmitted to the SRPLL via a 50-ohm RG316/U coaxial cable. A revolution tick is also supplied via a 50 ohm RG316/U coaxial cable.

To align the AGS with RHIC during injection the phase of the two machines is controlled as cogs on gears and hence the cogging reset. The RF for RHIC is synchronized to the AGS cycle. When they are synchronized injection may begin. To get into synchronization, the RF clock phase and revolution tick must be established or "reset" causing an arbitrary phase with respect to the previous RF phase and revolution tick. The SRPLL will get a revolution tick from the Synchro Synthesizer to determine the location of bucket 1, and it also gets a 28 MHz synchronous clock. The revolution tick is a single narrow pulse occurring at 78 kHz coincident with bucket 1. The RF clock will sweep with the RHIC ring RF and is the basis for all timing.

See the block diagram Fig. 5.

SRPLL reference switching operation: (Programmers take note)

First get an X-Terminal running. Then type "pet" at the prompt. Follow the tree FECS/LINKS/BEAMSYNC double click on "bssrPLL" (beam sync switched reference PLL)

This will bring up the start/stop and reference select control panel for the SRPLL.

PENTEK reference frequency setting: (Programmers take note)

First get an X-Terminal running. Then type "~joep/cnst18" this sets up some data base stuff for target 18 which is the fec used for this job.

Then type "pet"

Then find and click on the "File" button. A menu pops up with open. You must navagate the tree to

Ride/adoTree/systems/rf and run the file pentek-911-t18.pet

Then put the frequency button into manual mode

Then set the first frequency to the desired baseline input frequency. For a gamma of 10.24 you need about 14.001 MHz as the baseline. An exact calculation can be found in the EXCEL spread sheets.
 
 

Command and Control Shift Register:

This shift register is operated by setting pulses into the START REF and END REF inputs on the SRPLL. The trailing edge of a pulse sent to the START REF input will, after a zero phase match delay, switch the SRPLL to use whatever reference has been set in the command and control shift register (SR4 - SR1).

The trailing edge of the pulse sent to the END REF input will, after a zero phase match delay, switch the SRPLL to use the RF 28 MHz input clock from the Synchro Synthesizer.

To shift in a 1 into the shift register (SR1 - SR4) requires a CONCURRENT application of the pulses where the START REF pulse occurs first, and while still active, the END REF pulse occurs. See Fig. 1

To shift in a 0 into the shift register (SR1 - SR4) requires a CONCURRENT application of both pulses where the END REF pulse occurs first, followed by the START REF pulse. See Fig 2.

To start or stop the reference the START REF or END REF pulses are sent alone. See Fig 3.
 
 

1. Two V102 [output trigger module] outputs and two 50 ohm K-LOC patch cables are required to drive the START REF and END REF 50 ohm inputs.
2. START REF and END REF Pulses must be at least 50 nS wide to guarantee detection. These pulses should overlap by at least 50 ns to guarantee shifting. The phase lead or lag should also be at least 50 ns to guarantee the correct 0 and 1 detection. Typically phased pulses will be about 1 uS min in duration so this should not be a problem. Use the delay and pulse width settings on the V102 to send a phased pulse pair to the SRPLL on two channels. You will also have to create a 100+ms delay between the START and END falling (trailing) edges (non-overlapping pulses) to span the duration of the cogging reset. These channels must be set up to trigger on the cogging reset event, and also on software triggers to control the serially shifted data. If a single END pulse is set the SRPLL it will end the reference and lock onto the RF input. If sent again, the system will just continue to stay locked to the RF input. These inputs do not toggle individually. Since all V102 outputs are blind, and since the SRPLL inputs cannot be read back, re-sending the command is necessary to guarantee any particular state if the initial conditions or power history is not known. A frequency counter is necessary to determine if the correct reference has been selected during development and debug of the SRFF/V102 ADO. All 8 XTAL settings should be tested to select the proper XTAL. We will not have 8 different crystal clock oscillators at first, but we will observe the proper output enable pads on their sockets to verify exclusive selections, and that they are in the correct order.
3. There are 4 bits in this select control register( SR1-4). The first register bit shifted in is the most significant bit SR4 (most significant bit first convention), followed by SR3, SR2, SR1.
4. SR4 is the EXTERNAL DDS REFERENCE control bit which connects the DDS reference input to the PLL reference input. This overrides SR3, SR2, and SR1 settings. When high, the external DDS reference input is selected. When low "0" bits SR1 - SR3 select the INTERNAL XTAL REFERENCE.
5. SR3 - SR1 represent the OCTAL encoding of which one of the base line frequencies are selected to be used as the INTERNAL clock reference. ( Baseline frequencies are pre-programmed into a crystal based clock oscillator, and these baseline frequencies must be known and programmed in advance of their use. You will have 8 INTERNAL reference frequency choices if all the crystals are installed. The choice of frequency is dependent on machine physics, and the type of ions that will be used. For example, gold ions at baseline injection have been measured at 28.053581 MHz in the blue RHIC ring. This was the Longitudinal Machine Tune reported during commissioning. A frequency close to this will be placed into the 1^st XTAL position and is selected by shifting in a "0000" into SR1 - SR4. See Fig. 4.
6. To make the EXTERNAL DDS REFERENCE active shift in "XXX1".
7. Note you should always shift in 4 bits so as not to loose track of the shift pattern, even if the other bits are don't care (X). When you wish to use the EXTERNAL DDS REF, It is probably best to shift in all "1" as this will enable the 8^th XTAL, which is most likely not populated, which will lower the overall board noise contributing to jitter. At this writing we intend to leave the 8^th slot vacant. The INTERNAL XTAL references are "enabled" only one at a time from a standby low power condition which will take about 10 milliseconds to establish a stable output after being enabled. (The exact time is yet to be determined by measurements) Therefore it is necessary to setup or enable the correct XTAL quite a while before it is intended to be used. For any run, this shift operation causing one internal XTAL reference to be selected needs only be done once when the machine is being set up for a specific ion, or after a power interruption. The reference is then turned on and off with the START REF and END REF inputs. The shift register is designed to default to all zeroes on power-up. The default is EXTERNAL DDS REFERENCE with XTAL 1 (gold ion) selected. These power-up defaults can be programmatically changed depending on what default devices are needed as the application stabilizes and matures. Do not confuse the internal reference select/enabling with the start and stop functions. The start and end reference inputs take effect at the falling (trailing) edge of these signals. The enabling will take about 100 ms after the last bit has been shifted in for the XTAL to stabilize. This rather cryptic shift register approach is necessary to avoid having another VME interface on the SRPLL which must be galvanically isolated and RF shielded from the rest of the world. It requires only the two start and stop inputs to make it effective, and eliminates any jumpering that would be required to select the ion species.
8. In order to keep radiated and conducted RFI and EMI noise down inside the SRPLL to keep jitter down we only power up crystal sources when we select them through the shift register. Otherwise all 8 asynchronous crystal clocks would be running simultaneously. This would also increase significantly power consumption in the sealed (non-ventilated) RF enclosure. Since crystal clock sources have fairly long startup times, typically 10 milliseconds, we have to avoid introducing gaps into the reference output as the shift register is shifted. Programmers must be aware of a special precaution introduced into the hardware (logic). The logic implemented allows both the old and the new shift register selected crystal clock oscillators to be on simultaneously, that is until a START REF is issued. The reference output only changes when the START reference command is sent. This way the shift register shifts will not affect the reference output. It will power up only the appropriate decoded clock oscillator as each shift takes place (4 shifts for 4 bits would allow up to 4 clock oscillators to be decoded and powered-up sequentially, one on exclusively for each shift plus the old crystal which stays on). After the START REF command is issued only one (the new) crystal clock reference will be active. You should therefore assert a START REF command after each shift sequence whether you left the SRPLL in REFERENCE mode or not because the new reference clock oscillator will not take effect nor will the old clock oscillator turn off until you do. There are no apparent problems except for noise causing jitter by having two clock oscillators running which is be very difficult to debug. So make sure that you ALWAYS issue a START REF command after each and every time 4 bits are shifted in, whether it seems to work fine or not. This allows the startup time for the appropriate new clock oscillator to overlap with exactly one shift, the fourth (last) shift. This approach was necessary because we want to run the SRPLL when no RF clock is present (RF input mode cannot be used to mask out the gaps while shifting if no RF clock is available). Any DC transients on the reference clocks when in reference mode will cause major excursions on all the receiving PLLs and all types aberrant behavior would flourish. Simply put; we will switch the output frequency only upon a Start REF pulse. Both the old and the new oscillators will be running after a shift pulse pair is issued. The old oscillator will turn off, and the new oscillator will be switched to the reference clock immediately after a start pulse is issued. This will allow both oscillators to run, the old and the new concurrently for a minimal 10 ms startup period before the switch over takes place on the start command. We rely on the programmer to ensure the required 10 ms wait after the last bit is shifted in before issuing a START REF command pulse to allow the clock oscillator to stabilize. Fig. 6 below shows the proper clock sequence for selecting XTAL 8 and the falling edge of the start pulse which makes it active.

The INTERNAL REFERENCE crystal clock oscillators may be programmed to within 100 ppm of any desired frequency between 1 MHz and 106 MHz at this writing. The INTERNAL REFERENCE was necessary as the originally intended PENTEK 1420 EXTERNAL REFERENCE cannot supply low enough jitter for our application as originally envisioned. The external reference is tunable which gives us the flexibility which we desired, but its output has high jitter because the TTL comparator works on a sine wave that is generated, and on-board noise switches on the zero crossings with timing error. The PLL in the SRPLL will take a good deal of this jitter out, but the old adage holds true: garbage in - garbage out.

In an attempt to minimize our exposure to this noise, we put in the less flexible INTERNAL XTAL references which have about 250 ps pk-pk jitter, which will also be reduced by the PLL in the SRPLL, which will guarantee less jitter than the PENTEK 1420 can produce, with the disadvantage of less flexibility. The reference will only be used when there is no beam, so interactive tuning is not all that important. It is important however to keep the beam sync system running near the ion species baseline injection frequency to avoid causing transients that interfere with downstream beam sync system components that may not be able to track the rate of the frequency change.
 
 

Programmable Chip information:

(RD preliminary)

Altera EPM7064AETC44-10 PLD94028797 -

D:\kerner\rev_tick_xtal_shift3.dir\fastzero2.gdf

Switches on zero phase between the various crystals and the DDS reference which are inputs to this device.

D:\kerner\rev_tick_xtal_shift3.dir\rev_tick_xtal_shift3.gdf

This is the top level drawing containing both chips, and interconnections, and system level simulation.

Altera EPM7064AETC44-10 PLD94028811

D:\kerner\rev_tick_xtal_shift3.dir\shifter.gdf

V102 compliant serial receiver, and crystal selection chip. Powers up only one xtal at a time to reduce noise. During the switching interval, two crystals are powered until zero phase is complete, then the old crystal is powered down.

Altera EPM7128ATC100-6 PLD94028800

D:\kerner\rev_tick_xtal_shift3.dir\pld94028800

Switches on zero phase between RF input and any reference crystal or DDS. Controls PLL lock and jitter. Contains two frequency phase comparators a multiplexer a zero phase comparator and "no lock" logic for the LED.
 
 

Programmable PLL clock oscillator frequencies, gamma:

XTAL 1 EPSON SG-8002JA-28.016373-SCC, g = 10.25 (gold @ injection)

XTAL 2 EPSON SG-8002JA-28.147792-SCC, g = 70.00 (gold)

XTAL 3 EPSON SG-8002JA-28.149257 -SCC, g = 100.0 (gold)

XTAL 4 EPSON SG-8002JA-28.T.B.D -SCC, (blank)

XTAL 5 EPSON SG-8002JA-28.T.B.D -SCC, (blank)

XTAL 6 EPSON SG-8002JA-28.T.B.D -SCC, (blank)

XTAL 7 EPSON SG-8002JA-28.T.B.D -SCC,(blank)

XTAL 8 EPSON SG-8002JA-28.T.B.D -SCC,(blank)

XTAL 9 EPSON SG-8002JA-28.05388-SCC, g = 12.07 (gold ion window center)
 
 
 
 

Appendix

Jumper Table, MMCX cable connections.

J2 - START REF IN

J11 - 14 MHz DDS IN

J12 - REV TICK IN

J13 - RF 28 MHz IN

J14 - END REF IN

J15 - 56MHz OUT

J16 - 28MHz OUT

J17 - REV TICK 1 OUT (TTL)

J18 - REV TICK 2 OUT (LVTTL)

JP1 - interlock jumper (remove jumper before programming, replace after programming) for U15 PLL

JP2 - interlock jumper (remove jumper before programming, replace after programming) for U24 & U26

JP4 - insert on pins 2 & 4

JP2 - Solder a wire between pads. ( Wire shunt for AGNDISO to GNDREF )

JP3 - Solder a wire between pads. ( Wire shunt for GNDREF to DGND )
 
 

REV X PWB MODIFICATIONS:

LIFT the following pins before soldering pins to PWB:

U24P40

ADD the following 7 wires to the REV X PWB:

U26P43 - U24P11

U26P35 - U24P38

U26P8 - U24P40

U26P10 - U24P35

U26P34 - U24P39

U26P33 - U24P31

U5P55 - DS2

These modifications allow proper power-up and power-down sequencing for the on board crystal references, allowing only one to be powered at a time and ensuring a smooth transition and power overlap during the zero phase switching interval.
 
 
 
 
 
 

NOTES:

1. Only one thing so far has caused any problems with the beam sync link: Discontinuities in the RF clock have caused all the problems that we have encountered except for one: The jerry rigged PLL boxes had no output driver, and the Altera chip was ill suited to drive a 50 ohm load, so the outputs became intermittent due to thermal stress. We put a resistor in series to reduce the load current for the time being which clears up this problem.
2. We can use an event code on the V102 to switch to injection or storage frequencies if we are at injection or storage frequencies. The SRPLL can track at a fast rate. With the zero phase comparator switch, it will not slip 90 degrees when switching up a 42 kHz delta. Regular V124 PLL receivers are not as quick, and may still loose lock. Therefore it is best to try to match to within a few kHz before switching. If the frequency spread is larger, you must use the DDS to create a down ramp that we can all live with. (All V124s). The RHIC frequency spectrum is about 150kHz. If we need to avoid a storage to injection frequency nanosecond jump, we will have to first switch the SRPLL to EXT REF mode and bring it down using our own DDS. This will require programming time.
3. We found out in PHENIX that if the phase shift was about 36 degrees maximum error, the G-Link receivers would loose lock. I made a better zero phase comparator to get the zero phase error down to about 4 ns (14 degrees max error) which cleared up the problem. This means that the G-Link receivers are indeed very sensitive and they would not have run properly off of the beam sync system or for that matter off of a simple programmable clock oscillator with relatively small amounts of jitter and frequency drift. This underscores the need for the PLL after the PENTEK DDS and a PLL at the receive side.
4. Even though the V124 PLL receiver is not as quick as the SRPLL in tracking, the SRPLL will reduce the transients. This may be enough for the V123 to continue tracking.
5. We don't know just how big a frequency delta is necessary for the V124 to loose lock or generate bad output code. We should try it with the DDS driving the SRPLL which drives the V123, and the V123 drives a V124. Then by adjusting the input DDS instantaneous frequency jump, you can tell what will be acceptable in the field for the RF generator. The frequency discontinuity may be about 1 kHz to 42 kHz at 28 MHz which primarily depends on the phase only comparator gain and the PLL loop time constant. The loop time constant cannot be increased, as most people believe without severely increasing the output jitter. Tested 6/9/00 to be O.K. on both SRPLL and V124 PLL up to +- 40 kHz instantaneous switching.
6. We selected 3 crystal frequencies, gamma 10.25 @ 28.016373 Hz, gamma 70 @ 28.147792 Hz, and gamma 100 @ 28.149257 Hz. These will be crystals 1, 2 and 3. The other crystal choices will be left blank.
7. To help in diagnostics, the PLL>REFS and PLL>RF green LEDS are both turned on full when the crystal choice is outside a 2x or 1/2x range. When this happens, the old reference remains in effect, and you must send another crystal choice.
8. You can't switch from RF into a dead reference, or from a REF into a dead RF. But you can switch out of a dead RF into REF and out of a dead REF into RF if they are within the 2x or 1/2 x window. The PLL NO LOCK will illuminate whenever the frequency is outside the 7% frequency window. If you attempt to switch into a dead input you will have to switch back to a live input or reference first before trying again. If the input DDS or RF conditions (frequency window) fails within a small time delay the input will not attempt the switchover any longer to prevent noise from eventually looking like a good input. This will not affect the phase match delay which can be infinitely long.
9. To prevent a lockout situation, you can select any live reference within the 2x or 1/2x window as long as you stay in reference mode. In testing with fixed frequency crystals we were able to lock at 20.47 MHz and 38 MHz even though the NO LOCK LED was illuminated by the 7% frequency window.