1.0 V192 BOOSTER EXTRACTION START GATEMODULE

`V192/V193`

`V192 BOOSTER EXTRACTION START GATE MODULE`

`V193 RHIC 720Hz Module`

`Revised March 25, 1997`

Index
1.0 V192 Booster Extraction Start Gate
1.1 Introduction
1.1.1 New AGS Timeline
1.2 V192/V193 VMEbus Interface
1.3 V192 Extraction Start Gate Logic
1.4 V192 Jumpers
2.0 V193 RHIC 720Hz Module
2.1 Introduction
2.2 V193 Jumpers
3.0 Theory of Operation
3.1 V192/V193Module VMEbus Interface
3.2 V192/V193 Logic (PLD214)
3.2.1 V192 Booster Extraction Start Gate Logic
3.2.2 V193 720 Hz Logic
3.2.3 VMEbus Interface Logic
3.2.3.1 Registers
3.2.3.2 Interrupts
3.3 V192/V193 External Interfaces
3.3.1 Front Panel Input/output Connectors
3.3.2 Led Displays

V192/V193 Module SN 3, with VME interface installed for testing,
modules SN 1 & 2 don't contain the VME interface.

`1.0 V192 BOOSTER EXTRACTION START GATE MODULE`

`1.1 Introduction`

The V192 extraction start gate, and V193 720 Hz modules have been combined on a single VME module.

The V192 extraction start gate is used to control the Booster event code, extraction start gate, XTRN_ST, on the AGS timeline. The Booster extraction start gate is passed to the AGS timeline on machine cycles which start with Supercycle Generator event codes BT[1..4], and blanked on all other cycles The extraction logic may be jumpered to always pass XTRN_ST.

The V192 module was required following the Summer-Fall 1996 consolidation of the AGS timeline. Prior to that time there were separate AGS and Gauss timelines. The consolidation eliminated the serial output modules of the Multibus AGS Realtime and AGS Gauss chassis. The extraction start gate logic was a function of the Realtime serial output module.

The V193 720 Hz module is used to provide a 720 Hz clock for the V115 wave form generators, and lower frequency clocks to control time stamp functions. The 720 Hz logic includes external clock and synchronization inputs.

`1.1.1 New AGS Timeline`

Building 911B AGS Realtime and Gauss event chassis output modules were converted from serial to parallel. These modules replaced the original serial output modules. The AGS Realtime and Gauss parallel outputs are buffered by V198 VME modules, and decoded by V197 VME modules. Each V197 decodes 16 event codes, and provides 16 output strobes capable of driving a 50 termination. The V197 module outputs are patched into the AGS timeline chassis. The AGS timeline chassis is similar to the RHIC timeline chassis. The AGS timeline chassis outputs a single serial bi-phase-mark timeline that contains both AGS Realtime and Gauss event codes.

The Supercycle Generator outputs a standard serial bi-phase-mark timeline that contains 32 event codes. The event codes are decoded by two V196 VME modules. Each V196 decodes 16 event codes, and provides 16 output strobes capable of driving a 50 termination.

The Booster timeline, is decoded by a single V196 VME module. The module currently decodes event code extraction start, XTRN_ST.The

V192 module was developed following the consolidation of the AGS timeline. The consolidation eliminated the Multibus serial output modules. The extraction start gate logic was located on the Realtime serial output module.

`1.2 V192/V193 VMEbus Interface`

The V192/V193 module is a 4HP x 6U VME module. The V192/V193 module obtains power from VMEbus P1 and P2, and power-on-reset, SYSRESET*, from VMEbus P1. VMEbus P1 IACKIN-IACKOUT, and BG[3..0]IN-BG[3..0]OUT are wired in the PWB to maintain VMEbus daisy chain continuity. No other connections are made to VMEbus P1 and P2.

The V192/V193 has provisions for a simple A16 D8(OE) VMEbus interface. However, the integrated circuit bus buffers have not been installed.

`1.3 V192 Extraction Start Gate Logic.`

The V192 module inputs are BT[1..4] and BGE decodes from the Supercycle serial V196 decoder module, and XTRN_ST decode from the Booster timeline V196 decoder module.

BT[1..4] and BGE are XTRN_ST gate control inputs. BT[1..4] enable the gate, and BGE resets the gate if it occurs before XTRN_ST. XTRN_ST passes through the gate if enabled, and is blanked if the gate is disabled. If the gate is enabled, and XTRN_ST occurs, the trailing edge of XTRN_ST resets the gate. Two jumper patches control the extraction gate logic.

`1.4 V192 Jumpers`

There is a jumper patch area on the V192/V193 module. One V192 patch enables the logic, and the other controls the XTRN_ST gate or bypass function.

`V192 JUMPERS`
`LOCATION`	`JUMPER`	`FUNCTION`
`JP12`	`ON`	`GATE ENABLED`
`JP12`	`OFF`	`GATE DISABLED`
`JP13`	`ON`	`PASS XTRN_ST`
`JP13`	`OFF`	`GATE XTRN_ST`

V192/V193 Patching diagram

`2.0 V193 RHIC 720Hz MODULE`

`2.1 Introduction`

In RHIC building 1004B, the main power supply supplies a 720 Hz clock synchronized the mains 60 Hz. When this signal is detected, the V193 logic switches its 720 Hz output from its local crystal clock to the external input. The 720 Hz clock is divided to provide 60 Hz, 10 Hz, 1 Hz, and 1, 5, and 10 second ticks. The outputs derived from the 720 Hz clock are not synchronized to mains 60 Hz, etc. If the power supply 720 Hz is lost, the V193 will automatically switch to its internal crystal clock. In AGS building 911B, V193 crystal clock provides the clock source. The crystal clock divider can be set to 720 or 1000 Hz. The 720 Hz clock is divided to provide 60 Hz, 10 Hz, 1 Hz, and 1, 5, and 10 second ticks. When the 1000 Hz clock is selected, the 60 Hz output is not available. The AGS 720 Hz clock divider which supplies 60 Hz, 10 Hz, 1 Hz can be synchronized to a pulse input, SYNC. SYNC resets the 720 Hz clock divider, but doesn't reset the 5 and 10 second ticks.

`2.2 V193 Jumpers`

There is a jumper patch area on the V192/V193 module. One V193 patch enables the logic, and the other controls the basic clock.

`V193 JUMPERS`
`LOCATION`	`JUMPER`	`FUNCTION`
`JP14`	`ON`	`CLOCK ENABLED`
`JP14`	`OFF`	`CLOCK DISABLED`
`JP15`	`ON`	`1 KHz BASE CLOCK`
`JP15`	`OFF`	`720 Hz BASE CLOCK`

`3.0 THEORY OF OPERATION`

Reference:
     D36-E1455 Module Assembly - V192 Booster Extraction Start Gate
Module
   D36-E1451 Schematic Diagram - V192 Booster Extraction Start Gate
Module
     D36-E1452 PWB Drilling - V192 Booster Extraction Start Gate
Module
     D36-E1453 PWB Assembly - V192 Booster Extraction Start Gate
Module
     D36-E1454 Front Panel Drill & Screen - V192 Booster Extraction
Start Gate Module
   PLD214 Booster Extraction Start Gate
     NOTE: The V192 printed wiring board design includes three
functions:
           V192, V193, and VME interface. Normally only the V192 and
V193
           functions are included.

`3.1 V192/V193Module VMEbus Interface`

The V192/V193 module obtaines power from VMEbus P1 and P2 connectors, and initialization, SYSRESET*, from the P1 connector. The module VMEbus P1 connector passes IACKIN to IACKOUT, and BG[3..0]IN to BG[3..0]OUT for VMEbus compatibility. The module has no other VMEbus connections.

The V192/V193 printed wiring boards have traces for a VMEbus intereface, however the integrated circuits are not installed. The VMEbus interface is designed to support a simple A16 D8(OE) VMEbus interface. The interface is described in paragraph 3.2.2.

`3.2 V192/V193 Logic (PLD214)`

PLD214 U7 is an Altera EPM9320LC84-3. The 320 macro-cell EPM9320 far exceeds the logic requirements of the V192/V193, however it provides for future design changes such as a 500 Hz AGS clock base rather than 1 KHz. It also allows future development of a VMEbus interface with 8-input, and 8-output buffer/drivers.

PLD214 U7 is driven by an external 16 MHz TTL crystal oscillator, U4. The 16 MHz input is assigned to one of the EPLD global clock inputs. The clock is used by both the V192, and V193 circuits.

`3.2.1 V192 Booster Extraction Start Gate Logic`

The module front panel inputs are isolated by 6N137 optical isolators. The outputs of the optical isolators are /INPUTS[8..1] to PLD214 U7. The inputs are registered by global(16_MHz) clock in EPM9320 I/O cell flip-flops. The input expression is:

     NOT_INPUT_BUFFER[8..1].d = /INPUT[8..1];
     NOT_INPUT_BUFFER[8..1].clk = global(16_MHz);
     NOT_INPUT_BUFFER[8..1].clrn = /SYSRST;

Six of of the 8-inputs, NOT_INPUT_BUFFER[8..1], are used by the booster extraction start gate logic. The function of the booster extraction start gate is to pass Booster event XTRCN_START (shortened to XTRN_ST on the front panel), under certain conditions:

If V192 feature disabled, J12 OFF, never pass XTRN_ST.
If V192 feature enabled, J12 ON, pass XTRN_ST if:

J13 OFF and GATE present.
J13 ON GATE always on, always pass.

If the extraction start gate logic is enabled, gate flip-flop, GATE, is set by inputs BT1 # BT2 # BT3 # BT4, and cleared by BGE or the trailing edge of XTRN_ST. The inputs BT1, BT2, BT3, BT4, and BGE are INPUT[1..5] respectively. BT[1..4] are derived from supercycle events 0x0F, 0xF1, 0x19, and 0x1A respectively which occur near the start of an AGS cycle. These inputs if present set the gate. If GATE is set, XTRN_ST, is passed to the module output EV11H. As XTRN_ST is output, its trailing edge triggers one-shot GATE_OS[1..0]. When GATE_OS[1..0] == b"10", GATE is reset. If no XTRN_ST occurs before BGE, BGE resets the GATE flip-flop near the end of the AGS cycle. GATE is forced set if JP13, MODE1, is installed.

    GATE.prn = !(!/MODE[1] & !/MODE[0]); %J13 & J12%
    GATE.d = VCC;
    GATE.clk = BT1 # BT2 # BT3 # BT4;
    GATE.clrn = !(GATE_OS[1] # BGE) & /SYSRST & !/MODE[0];

The V192 output expression:

    EV11H = XTRN_ST & GATE;

`3.2.2 V193 720 Hz Logic`

PLD214 U7 is driven by 16 MHz TTL crystal U4. Clock divider, 16_DIVIDE[], divides the global(16_MHz) input to produce 720Hz or 1KHz. The divisor is controlled by JP15, MODE[3]. The internal counter 16_DIVIDE[] may be synchronized to external input INPUT[8], SYNC. The divisor "IF" statement is:

if SYNC_OS[1] == 1 & /MODE[3] then 16_DIVIDE[] = 0;              
%sync 720 Hz%
   elsif SYNC_OS[1] == 1 & !/MODE[3] then 16_DIVIDE[] = 6222;    
%sync 1000 Hz%
   elsif 16_DIVIDE[] == 22221 & /MODE[3] then 16_DIVIDE[] = 0;   
%720 divide%
   elsif 16_DIVIDE[] == 22221 & !/MODE[3] then 16_DIVIDE[] =
6222;%1000 divide%
   else 16_DIVIDE[] = 16_DIVIDE[] + 1;                           
%both%
end if;

The divisor is controlled by two external signals, /MODE[3] and /INPUT[8]. /MODE[3], JP15 , jumper OFF the basic clock is 720 Hz, if ON 1000 Hz. The divisors are 22221 and 16000 respectively. /INPUT[8], SYNC, is synchronized, and converted to a single 16MHz pulse in one-shot SYNC_OS[1..0]. If SYNC is active, 16_DIVIDE[] is reset on the leading edge of front panel input SYNC. SYNC is normally an AGS operating function, synchronize the clock divider to AGS T0. The output of 16_DIVIDE[] is input to one-shot, OS[1..0], along with the front panel external clock INPUT[7], normally 720 Hz in RHIC. The one-shot input is controlled by SELECT. If asserted, SELECT, selects the external input, if negated, the output of 16_DIVIDE[]. The output of OS[1..0], a single 16MHz clock is stretched by one-shot OS[5..2] to 1 microsecond CLOCK_OUT. CLOCK_OUT is output from the EPLD and looped back as global(CLOCK_IN). Global(CLOCK_IN) is always present, even if /MODE[2] input jumper JP14 is OFF. Global(CLOCK_IN) is used in the LED display circuits.

Global(CLOCK_IN) is divided by 720 or 1000 in CLOCK_DIVIDE[], the divisor controlled by MODE[3]. The counter outputs are decoded by case statement:

case (AGS, CLOCK_DIVIDE[]) is
%720 Hz decodes%
   when h"000" => (SIXTY, TEN, ONE) = b"111";
    "
    "
   when h"2C4" => (SIXTY, TEN, ONE) = b"100";
%1000 Hz decodes%
   when h"400" => (SIXTY, TEN, ONE) = b"011";
    "
    "
   when h"784" => (SIXTY, TEN, ONE) = b"010";
   when others => (SIXTY, TEN, ONE) = b"000";
end case;

When the divisor is 720, the outputs are SIXTY, TEN, and ONE; 60Hz, 10Hz, and 1Hz. When the divisor is 1000, the outputs are TEN and ONE; 10Hz, and 1Hz. 60Hz not available, its not a multiple of 1KHz.

The outputs SIXTY, TEN, and ONE are registered in flip-flops SIXTY_HZ, TEN_HZ, and ONE_HZ. The flip-flops eliminates any case statement decoder output glitches. The flip-flops also synchronize the 720/1000Hz output to the lower speed clocks.

ONE_HZ is further divided to provide 5 and 10 second ticks. Outputs FIVE and TEN are also registered, flip-flops FIVE_SEC and TEN_SEC.

`3.2.3 VMEbus Interface Logic`

The VMEbus interface has been implemented to test the possibility of an interface, and reserve the EPLD logic for future modifications. The module address is completely determined external to EPLD U7. The input /MODULE indicates that a VMEbus short address exists within the module's 128-byte address block. On every VMEbus cycle which asserts DS0 $ DS1, shift register SR[4..1] starts to shift "ones". SR[], driven by global(16_MHz), controls the module VMEbus response time. First EPLD output /HOLD latches the VMEbus address A[06..01] as ADDR[6..1] in 74LS373 U11. At the same time ADDR[0] is latched in the EPLD. DS0 is essentially VME bus address A00 in byte mode.

Next EPLD input /MODULE is sampled. If !/MODULE & /IACK (not an \interrupt cycle), MODULE_ADDR is latched on the leading edge of SR[3]. As MODULE_ADDR latches, EPLD output /PROM_CS is asserted if the odd bytes of the VMEid are addressed. The odd bytes of the VMEid are contained in PROM U21. The PROM address is supplied by U11, and /PROM_CS enables the tri-state output of U21.

MODULE_ADDR triggers one-shot SELECT. SELECT drives the the front panel VME SELECT LED for one cycle of global(CLOCK_IN).

MODULE_ADDR, /DS1, and /DS0 control EPLD outputs /HI_ENA and /LO_ENA. These two outputs control 74LS645-1 bi-directional buffers U19 and 17 respectively. The buffers convert VMEbus D[15..00] into a byte interface. U19 drives VMEbus D[15..08], and U17 drives VMEbus D[07..00]. Both U19 and U17 are driven by the modules bi-directional byte data bus DATA[7..0]. /LO_ENA is also driven during an interrupt cycle, STATUS, to output the interrupt vector INT_VEC[7..0]. The direction input to U19 and U17 is VMEbus /WRITE. /WRITE controls the data transfer direction.

NOTE: 74LS645-1 is a high current version of the 74LS645. The -1 will sink the 48 ma required by the VMEbus terminators.

On the leading edge of SR[2], internal registers are latched if a VMEbus write cycle !/WRITE. While MODULE_ADDR is set in the /WRITE mode, the EPLD tri-state data bus DATA[7..0] is enabled by D_STATE[7..0] if EPLD registers are addressed.

Finally on the leading edge of SR[1], the VMEbus response, DDTACK, is set. The front end computer responds by clearing DS[1..0]. As DS[1..0] clear, the shift register and MODULE_ADDR ending the VMEbus cycle.

`3.2.3.1 Registers`

There are eight registers in the EPLD. INT_VEC[2..0] containes three bits, the remainder are byte registers. All registers are read/write except the status register which is read only. The registers are:

CR[7..0] command register, with CR[1..0] controlling interrupt and activity.
ST[7..0] status register, nothing assigned
REG[4..1][7..0] four registers, nothing assigned
INT_VEC[7..0] interrupt vector register
INT_LEV[2..0] interrupt request level

The registers are connected to an output multiplexer in the EPLD. The multiplexer, case statement:

case (STATUS, ADDR6, ADDR[3..0] is
  when b"00xxx0" => D_TSTATE[7..0].in = PERIOD[7..0];
   "
   " 
  when b"1xxxxx" => D_TSTATE[7..0].in = INT_VEC[7..0];
end case;

The two examples of the case statement above show two special cases. The first line shows the development of the ASCII period in the VMEid. The period is developed in the EPLD, and the text in PROM U21. The last line shows the interrupt vector, INT_VEC[7..0], which is output during the interrupt cycle. The statements in between are the eight register outputs.

`3.2.3.2 Interrupts`

Register CR[7..0] is connected to register ST[7..0] via a comparison for inequality CHANGE. CHANGE performs two functions: first, transfers the contents of the command register into the status register; and second, requests an interrupt. This configuration has little value, it just reserves the register elements. A practical use would be for status signal inputs to latch into status register, and request an interrupt on change-of-state of the status register.

CHANGE sets flip-flop IRQX. IRQX is output to 74LS138 U24 along with INT_LEV[2..0]. U24 decodes the interrupt level /IRQ[7..1], IRQ[0] is reserved by the front end computer. IRQX enables U24, and one output, buffered by 74LS641-1 U25 requests an interrupt IRQ[7..1]*. On the next assertion of /DS0 flip-flop LOCAL sets indicating a local module interrupt request.

NOTE: 74LS641-1 is a high current version of the 74LS641. The -1 will sink the 48 ma required by the VMEbus terminators.

The front end computer responds with an interrupt cycle which asserts /IACK. /IACK is distributed to every VME chassis slot to indicate an interrupt cycle in progress. At slot 1, /IACK loops back as /IACKIN-/IACKOUT, the interrupt daisy chain.

If the module receives /IACKIN, the interrupt timing shift register INT_SR[2..0] starts:

INT_SR[2] sets as /IACKIN is asserted.

delay one clock

INT_SR[1]

Set STATUS if requesting an interrupt LOCAL, and the request level equals the reply level, INT_LEV[2..0] == ADDR[3..1]. STATUS enables the INT_VEC[7..0] output on the tri-state bus D_TSTATE[7..0] (DATA[7..0]).

INT_SR[0]

Set IDTACK if requesting an interrupt LOCAL, and the request level equals the reply level. IDTACK, the interrupt acknowledge logic ORed with DDTACK to form output /DTACK. /DTACK is buffered by 74LS641-1 U25. The front end computer completes the interrupt cycle by clearing /DS0. This clears IRQX, LOCAL, STATUS, IDTACK, and the INT_SR[2..0].
Set /IACKOUT if not requesting an interrupt or the request level doesn't equal the reply level. When the host computer completes the interrupt cycle, /AS clears /IACKOUT, and /DSO clear the shift register.

`3.3 V192/V193 External Interfaces`

`3.3.1 Front Panel Input/output Connectors`

Front panel inputs labeled: BT[1..4], BGE, EXTRN_ST, 720_HZ, and SYNC are isolated by HP 6N137 optical isolators. The Lemo connectors, terminators, and 6N173 input are on a separate ground plane AGND. AGND is connected to the front panel. The inputs are terminated in 50 ohms. The 50 ohm termination is comprised of a 24 and 36 ohm resistive voltage divider, with the 6N137 optical isolator connected across the 36 ohm resistor. When the optical isolator diode is conducting, the termination is approximately 50 ohms. Each 6N137 LED has a diode across its input suppresses to reverse voltages. The 6N137 optical isolators contain a simple, open collector, TTL gate, therefore the inputs to the EPLD /INPUT[8..1] are inverted.

EPLD outputs PULSE[8..1] are buffered by TI SN75130N U9 and U14. The SN75130N is designed to drive four 50 ohm terminators to greater than +3VDC. The SN75130N also contains built-in short circuit protection. Lemo output connectors are located on a separate ground plane. The plane may be connected to DGND, JP16, or AGND, JP17. The outputs Lemo of U9 and U14 are terminated in 470 ohms. The 470 ohms terminator provides a scope trigger if the output is not used, and will not disturb the 50 ohm line termination.

`3.3.2 Led Displays`

EPLD output /SELECT directly drives the front panel VME SELECT LED.

The sixteen LEDs located under the Lemo connectors are registered to stretch the pulse lengths, and multiplexed to conserve pins. NOT_INPUT_BUFFER[8..1] trigger eight one-shots INPUT_REG[8..1][1..0]. The one shot clock is LED_DISPLAY[3]. Gate and time outputs trigger one-shots OUTPUT_REG[8..1] which are also clocked by LED_DISPLAY[3]. LED_DISPLAY[3..0] is a 16-bit counter driven by global(16_MHz). The count provides a LED on time of 1.4 ms when the 16-channel multiplex is considered. Within the EPLD, the display LEDS are multiplexed by case statement:

case LED[3..0] is
  when 0 => /LIGHT = !INPUT_REG1[1];
    "
    "
  when 15 => /LIGHT = !OUTPUT_REG[8];
end case;

EPLD outputs LED[3..0] and /LIGHT drive the LED displays. LED[3..0] drives 74LS138 decoders U18 and U22. /LIGHT enables U18 or U22 if the LED associated with the current multiplexer state should be illuminated. U18 and U22 decoder outputs drive 74LS641-1 buffers U20 and U23. U20 and U23 drive the LED indicators.

All LED indicators have built in resistors.