Brookhaven National Laboratory
Accelerator Control Systems
Associated Universities, Inc.
P.O. Box 5000
Upton, L.I., N.Y. 11973-5000

T. Kerner

Rev. 0.0 Scalers.doc Jan. 16, 1996
Rev. 0.1 Scalers2.doc Mar 25, 1996, register descriptions and locations.
Rev. 0.2 Scalers3.doc Apr. 28, 1996, changed register names and locations for best Altera fit, modified addressing examples, added address jumper configuration examples.
Rev. 0.3 Scalers4.doc April 7, 1997, continued addressing description, and functional description of register bits, and FIFO contents.
Rev. 0.4 Correct typos in the register names and the register addresses. Correct read from FIFO
description when FIFO is empty, and some minor typos.
Rev. 0.5 September 19, 1997. Changed order of Timestamps and Gate count to reduce probability of causing metastable conditions between gate rising edge and FM clock.

Editorial changes:
Rev. 0.6 October 7, 1997. Removed all references to BPM system objective and design guidelines to generalize the module for other uses. Added tutorial on metastability, astability and race conditions, and how these conditions are avoided using this scaler.
Rev. 0.7 October 16, 1997. Improved register table descriptions, modified acronyms for uniformity, included enabling register names. Added alphabetically arranged acronym table with definitions and descriptions. Tables now show real time and occurrence read capabilities. Made HTML file.

Rev. 0.8 November 13, 1997. Sclaers8.doc Changed section order, add a convenience 4.4MHz restriction, remove addendum, put electrical specs in tabular format.

Rev. 0.9 November 18, 1997. Scalers8.doc. Changed T0 to timeline event reset fiducial in many places, removed multiply mapped segment explanatory paragraphs, and description of consequences of missing the FIFO read real-time deadline.

Rev. 0.10 December 5, 1997. Scalers8.doc. Changed timeline event reset fiducial to front panel fiducial or reset event in many places, removed paragraph detailing possible uses for EEPROM contents, added paragraph on actual EEPROM contents as supplied at time of programming.

 Rev. 0.11 December 29, 1997. Scalers8.doc. Delete paragraph on EEPROM programming.

The VME Scaler System uses counters to convert serial TTL level clocks, into a digital 24-bit count over a specified gate period. Each front panel input clock is TTL 50 ohms terminated. The scaler data are buffered and formatted with 31-bit 15 nS time stamps, 16 channels per module for distribution over the VME system backplane to the front end computer (FEC). The VME Scalers data are taken at intervals determined by an external gate. The VME V116 Scaler System is designed to provide maximum gate flexibility such that there are little or no limitations on counting FM data at maximum rates. Gate timing restrictions have been minimized by the use of high speed counters with latches to reduce the inter-gate timing delay to less than 1 mS. FIFO buffering permits over 3600 samples (215 gates) to be captured prior to VME bus service, permitting maximum multi-module system bus performance.

Provide a VME based scaler system to accept pulse trains which originate from a FM characteristic source. The Scalers shall count the rising transitions between a defined gating interval (frequency counting). Gating and reset may be applied by 50 ohm TTL Lemo external inputs. Closely spaced sequential gate intervals are supported. FIFO buffered memory will allow repetitive samples to be saved before being accessed by the VME bus host.

 2.0 VME Scaler Modules

• Sixteen fast (4.4 MHz - 50 MHz or time between rising edges no less than 20 nS) scalers per VME module.
• Each counter is 24 bits in magnitude, with prescaler, and counter overflow indication bit.
• Each counter has a 24 bit output latch to allow FIFO loads while gates are active allowing back to back multiple samples.
• Counter runs from 4.4 MHz to 50 MHz in direct coupled mode (short 50 ohm coax cable with Lemo). Back panel P2 connector differential inputs run to 25 MHz 50% duty factor (20 nS high, 20 nS low).
• FIFO capacity is 4K by 32 bits, providing dual port sequential access. (allows up to 215 samples of counter and timestamp data for all 16 channels before VME bus service is required .)
• Four prescaler choices: divide by 1, 5, 10, 100, selectable by VME bus register access.
• Timestamp 31-bit for gate leading and trailing edges in 15 nS increments, used for "bookmark" diagnostics, passed through FIFO. (32 seconds maximum readback, 64 seconds before overflow)
• FIFO data arranged as 24 bits of counter plus 8 bits of status (empty flag, ½ full flag, sequence ID bits 0-4, and overflow flag.)
• Gate count placed into FIFO before 16 scalers are loaded.
• Front panel reset FIFO and timestamp counter on fiducial (Lemo connector input.)
• VME bus addressing A24, with 256 base addresses selected by dip switches (64K spacing).
• Read/Write byte D08, D16, D32 access to command/status registers, D08 & D08 BLT, D16 & D16 BLT, D32 & D32 BLT burst access to FIFO.
• VME ID EEPROM. (D08(O) byte read access).
• FIFO full, half full, and empty status all with interrupts that may be enabled or disabled individually.
• Multiple repetitions of the selected gate periods may be placed back to back within 1 mS of each other.
• Minimum inter-gate spacing 1mS, and minimum gate duration 1mS, to allow FIFO load cycle completion.
• All 16 scaler channels have activity indicator LEDs and remote interrupt on change of activity status which may be individually enabled or disabled.

A common gate trigger input enables counters in parallel and causes the first timestamp register to be latched. The 16 counters’ contents and the second timestamp are latched upon termination of the input gate signal and then a state machine unloads the latched timestamps, gate count, and counter values into FIFO. The latches permit the next gate to start prior to loading of the 19 counter values into FIFO and/or to allow for slow FM clocks. Only the first timestamp and gate count must be loaded into FIFO prior to the beginning of the next Gate. This overlaps the FIFO loading operation with the scaler counting operation. As long as the counting operation takes longer than the loading operation, all proceeds as expected. The leading edge Gate timestamp and gate count are loaded first into the FIFO to allow the next gate to begin immediately afterwards causing a new value to be latched in this counter's output register. Should the input Gate timing be such as to violate the above, the leading timestamp will be lost, and an error overrun status will result. The counters are reset, and the next gate period may begin within 1 mS. The FIFO state machine will take 1mS to load the 19 counter values into the FIFO, so the duration of the gate must be at least 1mS if multiple gates are placed back to back to avoid data overrun. The counters must all be serviced before the output latches are ready to be loaded again on the trailing edge of the Gate. The loading of the FIFOs is done at the highest rate allowed by the components (22 MHz) without violating its input timing specifications. The fastest speed grade FIFO is used here to provide maximum performance.

Timestamp counters are running all the time with a 66.667 MHz (15 nS) clock. Both timestamp counters are 31 bits to allow for 32 seconds to pass after a front panel fiducial or reset event with full visibility to 31 bits on a timestamp read. The 32^nd bit is not visible as the overflow status is placed on this line. The actual counter size is 32 bits and will overflow in about 64 seconds. The most significant bit of the 32 bit counter is easy to infer by the approximate time between Reset and the time stamped gate edges. The timestamp counters are reset by the front panel lemo input fiducial or reset event and indicate for every gate edge thereafter. The difference in the two timestamps represents the length of the gate. Both edges of the Gate signal are timestamped to improve accuracy. The leading edge timestamp is latched by the first timestamp counter and the trailing edge timestamp is latched by the second timestamp counter. The timestamp counters do not reset with the input scaler counters with each gate, but are reset by the front panel lemo fiducial or reset event input such that a contiguous timing history may be included along with the scaler data for multiple samples within a cycle. The timestamp counters are reset by the front panel reset input, which can be any selected fiducial TTL 50 ohm signal including a timeline event which may be at the beginning or end of a cycle.

During a selected fiducial or reset event, the FIFO is reset to allow recovery from unfinished business during previous accelerator cycles. Therefore, programmers take note, a real-time constraint is placed on the lifetime of the data. A real-time deadline is imposed. All the data must be recovered from the VME bus accessible FIFOs before the occurrence of a fiducial signal arriving on the reset input. Also the data on the FIFO is tri-stated when the FIFO is empty, so expect random data from a read when the FIFOs are empty!

Each scaler counter is 24 bits in magnitude, and counts up in binary to a maximum decimal value of 16,777,215 before an overflow condition occurs which can be found in the scaler status field of the FIFO data, and in the proper occurrence status register. See VME Scaler Module Register Bit Definitions. The input to the counter may be prescaled by setting the proper control register bits. See section on VME Scaler Module Register Bit Definitions, input register programming. The choices are divide by 1, 5, 10 and 100. This extends the range of the scaler before it overflows, or may be used to eliminate least significant bits should the input FM signal have a lower accuracy say 18 bits.

FM signals are connected to the front panel Lemo connectors or differentially through the rear P2 connector. A single gate signal and reset signal are connected to the front panel Lemo connectors as well. The rear panel P2 connector has 32 pins in row A and C which are user defined to connect through the J2 backplane to a 64 pin IDC ribbon cable connector and ribbon cable. The A row of pins will be used to carry 16 pairs of differential signals. The C row will be used to carry the signal ground isolation wires to the module's P2 connector which is isolated from digital ground. The signal ground wires will be connected only at the source, and to one another, to prevent ground loops. Because of the individually unshielded nature and close proximity of the conductors in a ribbon cable, carrying asynchronous 10 MHz signals, it is necessary to use differential signals on this cable with proper impedance matching terminations on the receiving end of the transmission ribbon cable. The FM signals must be grouped differentially and isolated from one another by interspersing ground signals on the ribbon cable to allow for some crosstalk isolation. The choice of input from the front panel Lemo connectors or the P2 connector will be made by 4 jumpers which divides the scaler counters into two banks of 8 counters each. Each bank may use either front panel or P2 connector inputs.

The differential receivers on the VME Scaler board will use DS96F173CJ chips which are a high frequency version of the standard AM26LS32 EIA RS-422-A & EIA RS-423-A receivers. The DS96F173CJ chips meet EIA-485, EIA-422A, EIA-423 standards. The DS96F173CJ chips use L-FAST bipolar technology to increase operating speed while decreasing power dissipation. They are pin compatible with the AM26LS32. The DS96F173CJ chips have been tested to 25 MHz at 50% duty cycle (20 nS high 20 nS low) using a test jig and ribbon cable with AM26F31 differential drivers with heat sinks. The Gate and Reset signals are located on the front panel. See VME Scaler Module P2 User Defined Pin Specification.

The VME Scaler module will occupy one 4HP, 6U, 160 mm standard VME slot. It will have an aluminum front panel with conductive contact points to frame ground rails on the chassis, aluminum ejector handles, protruding Lemo connectors, and clearance holes for LED indicators. The panel will be powder coated with a non-conductive finish and silk screened with identifiers. The upper and lower handles will be labeled with the V116 module designation and ACS group designation respectively. The J1 & J2 VME connectors will be 96 pin Eurocard DIN 41612 Standard. The construction will be to commercial standards for the printed circuit card which will utilize a 6-layer PCB, 4 signal layers and 2 power planes with solid 1 oz. copper +5V and 2 oz. copper digital ground plane.

The VME Scaler Module was designed to operate with a supply voltage ranging from 4.80 V to 5.25 V. Supply voltage beyond these limits will hold the electronics in the reset state. The current will be approximately 4 amps per module with all inputs active at rated frequency and 2 amps quiescent.

Lemo (K-LOC) connector inputs

Input Clock Electrical Specifications (P2 connector):
4.4 MHz to 25 MHz on rear P2 connector, differential.

P2 connector inputs

Power requirements

Input Clock Electrical Specifications (Lemo K-LOC):
4.4 MHz to 50 MHz on front panel Lemo connectors.

Input Gate Electrical Specifications

Input Reset (fiducial or event reset) Electrical Specifications:

Handling requires ESD protected containers with ESD protection measures fully employed at all times. ESD protection is employed on all exposed surfaces once the module is properly mounted in its chassis.

Buffer surface temperature when all channels are driven at 50 MHz at 40° C ambient with forced air circulation.

Power dissipation is expected to be 25 Watts maximum and the module requires forced air circulation. Ambient temperature should not exceed 40° C. Surface temperatures of 60° C are not to be exceeded. The input buffer (50 MHz on all channels) thermal limit was set at 40° C, at 22° C ambient temperature, in a forced air cooled VME chassis with the front of the chassis open to ambient. ( This represents a reasonable worst case scenario.)

The VME Scaler Module may cause interference with some sensitive electronic systems. The module has no special EMI reduction preventative measures other than proper layout and proper grounding. No magnetic shielding is employed, and its module assembly does not utilize EMI leakage seals. All external cabling should utilize full shielding. Frame grounding is required on the VME chassis. There is no provision to prevent ground loops from occurring to the frame grounded chassis components and front panel. Cabling is therefore restricted between adjacent frame grounded racks or within the same rack.

• Green LED indicator (1) for Gate activity.
• Green LED indicator (1) for front panel fiducial or reset event input activity.
• Green LED indicators (16) for input FM activity.
• Green LED indicator (1) for VME access activity.
• Red LED indicator (1) for VME bus error.
• Red LED indicator (1) for Off Line status.

• Lemo single ended connectors (16) for FM inputs, 50 ohm terminated, TTL.
• Lemo single ended connector (1) for Gate input, 50 ohm terminated, TTL.
• Lemo single ended connector (1) for front panel fiducial or reset event input, 50 ohm terminated, TTL.
• P2 connector 16 differential FM 110 ohm terminated inputs, using 110 ohm impedance, shielded, transmission line rated and qualified ribbon cable assemblies.

The VME Scaler module shall have a standard slave VME interface which is compliant with and conforms to ANSI/IEEE STD1014-1987 IEC 821 and the Euroboard form factor IEC 297 electrical, mechanical, and functional specifications. The module will respond to supervisory and non-privileged standard BLT and data access address modifier codes 3F, 3D, 3B, 39

A24 addressing uses VME backplane signals A01 to A23. We can jumper program our V116 with up to 256 base addresses, by installing and/or removing eight jumpers according to the address table. This means each board occupies a total of 64K bytes of address space. This address space is further divided into four 16K segments on each board. The first 16K segment belongs to the read/write EEPROM, the second 16K to read only status, the third 16K to read/write status/control, and the last 16K to the read only FIFO.

Since not all of the 16K of each address segment is used, these areas are multiply mapped within the segment. In other words, in the 2K X 8 EEPROM segment, the EEPROM can be accessed from start to finish eight times within its 16K space, meaning the most significant 3 bits of this address segment A13 - A11 are effectively ignored. The sequential bytewise ascending order FIFO interface which uses four 4K X 8 FIFOs in parallel may actually use all of the 16K of sequential addresses in this segment if 4K of data is already in the FIFO when we start reading and 12K more is written while we read. The 4K FIFOs then can map into a virtual 16K address space! Programmers take note; the routine vmeMap which searches the entire vme address space looking for addresses that respond with a DTACK* to a single byte read, will undoubtedly report an incorrect size or miss the whole FIFO region due to reception of BERR*s generated by the required bytewise ascending sequential order monitor interface. It should also be noted that each and every time this routine is invoked, (or any other operation that reads a FIFO byte just for looks-see), necessitates resetting the FIFOs through the control register interface. Specifically running the "vmeMap" routine twice after a system reset causes the FIFO region to disappear! We will as a matter of convention, always access each device in each segment at its first (lowest) multiply mapped address. The FIFOs must be addressed at their lowest segment address after a reset or retransmit. The 2K EEPROM device holds the current VMEID string of 32 bytes: (Subject to change)

followed by the current board configuration settings, full application name and references to on-line documentation: (Subject to change)

Following is the current configuration & maintenance Altera chip revisions and checksums in the following format:

Device number in JTAG chain, reference designator, user code, PLD #, chip name, checksum, programming file compilation date, version of Altera compiler used, and chip revision. (Subject to change.)

Device 11 U27-U42 226 CNT24A8 000c0a33 09/15/97 V7.2 REV A.00

With the address jumper installed [:] the bit is set to zero, and with it removed : the bit is set to one. Since there are 256 possible base addresses, only 16 representative sample addresses are shown in the following table. Holding the PWB with the JP5 jumper block at the top, the A16 to A23 jumpers are in the following order:

JP5

The 16K r/w EEPROM segment starts at the base address + 0X0000 and ends at base address + 0X3FFF, note only 1/4 of this segment (ba+0X0000 to ba+0X0FFE) is used by the 2K EEPROM. And that this segment is D08(O) so that byte 2 and byte 4 are inaccessible.
The 16K read only STATUS segment starts at the base address + 4000
The 16K r/w COMMAND/STATUS segment starts at the base address + 8000
The 16K read only FIFO segment starts at the base address + C000
Further examples:

D32 FIFO access (using only quad byte access)

After a power up reset or a remote register reset or retransmit, to simultaneously read the first four FIFO bytes from the first V116 as addressed in the above table, using jumper base address F010 XXXX and the C segment at address F010 C000, the very next quad byte transfer address must then be F010 C004 to avoid a bus error. During a quad byte transfer, all four byte counters increment on each access.

D16 FIFO access (using only double byte access)

After a power up reset or a remote register reset or retransmit, simultaneously read the first two FIFO bytes from the first V116 as addressed in the above table, use address F010 C000, the very next double byte transfer address must then be F010 C002 or F010 C004 to avoid a bus error. During a double byte transfer, only two byte counters increment on each access. This means you may extract all bytes from the first and second byte FIFOs before pulling any data from the third or fourth byte FIFOs. This is not recommended however, because it is too easy to lose track of your accesses and you may generate a bus error for attempting to access data out of bytewise sequential ascending order.

D08 FIFO access (using only single byte access)

After a power up reset or a remote register reset or retransmit, to read the FIFO from the first V116 as addressed in the above table, you may access any of F010 C000, F010 C001, F010 C002, or F010 C003 as the first single byte access without a bus error. Say you chose F010 C000 as the first byte then, the next single byte address must be one of (F010 C004, F010 C001, F010 C002, or F010 C003) to avoid a bus error. Say you choose F010 C003, then the next byte address must be one of (F010 C004, F010 C001, F010 C002, or F010 C007). I hope you see the progression of the ascending byte counters in this example. It helps to keep four running totals of the four byte counters if you choose to go out of purely bytewise ascending address order!

The simplest transfer is the D32 BLT, because all bytes are guaranteed to come out in ascending sequential order!

REGISTER TABLE:

Note: All except one of the registers use active high (1) logic. Inputs to registers from the board may be activity change triggered or rising or falling edge triggered depending on the fixed hardware requirements as related in the register descriptions. Setting an interrupt register bit enable makes the corresponding interrupt register active and clearing an interrupt enable register will disable the corresponding interrupt register. Data read or written from the VME bus registers will always be positive true high (1) except for the OFF-LINE status bit which must be active low (0) when powered up, and set to high (1) when disabled or turned off.

It should be noted that an interrupt pending (IP) function is a real time control function, and an occurrence (OC) function is a register storage function which remains set until reset by human intervention (manually observed and cleared for diagnostic purposes). The two are very different. The interrupt pending function interfaces with the FEC to cause an interrupt service routine which then clears the pending interrupt. The pending logic may set and reset in mS, and is used to trigger the occurrence register which will remain set until a diagnostic operation resets it possibly days, months, or years later. This way you can find out if any occurrence has taken place since the last time you looked. This is a good diagnostic feature. An example of an occurrence operation would be to query if any BERR*s were generated by the board since the last time the system was reset or powered on. It should also be noted that error and information statuses have different meanings. An error (ER) class status indicates some intervention by the programmer (system software) or user is necessary to prevent and/or resolve a problem which is occurring, such as an input channel cable being disconnected requiring a red flag being placed on that channel’s data acquisitions, and a service call to repair the cable must be made. An information (IN) class status can be used to diagnose the operation of a functional system, such as knowing that block transfers are being used correctly without generating BERR*s or that data is being collected a byte at a time from the FIFOs properly by VxWorks without violating bytewise ascending sequential order rules. A command (C) function is used to control the hardware. Some commands such as the user preset status/ID interrupt vector or the prescale divide setting are held in effect until changed. Other commands are transitory (T) and terminate at the end of the write cycle such as FIFO retransmit and reset functions.

Acronym Alphabetically Ordered Key and functional description.

OCELAC01 – OCELAC16 - Occurrence, Error, Local Activity Change, channel 1-16.

These diagnostic registers are read/write. There is one input activity change status register for each of the 16 input channels. These diagnostic registers are set at each activity change detection, and are reset only by a diagnostic routine or by direct register clearing. An interrupt pending (IP) error is signaled each time the "carrier" is lost or re-established, such as when a cable is first connected or disconnected, and is serviced by the interrupt service routine. The occurrence (OC) registers provide an after-the-fact diagnostic capability. Activity is sampled between consecutive front panel reset fiducials or events. If a line is active and stays active after each reset, then no activity change is detected. Any rising transitions on a scaler input between reset samples indicates activity for that channel. If the appropriate channel interrupt enable bit is set, and if the global interrupt enable bit is set, and if the interrupt priority level is set to something other than zero, then the input activity change will generate an interrupt. The interrupts may be used to notify the processor to ignore disconnected channels by red flagging the data or to monitor newly connected scaler channels, which can create a dynamic connection table. Only 1 interrupt is sent for each input line activity "carrier" change. The real-time monitoring of input connectivity is done by the corresponding interrupt pending (IP) registers. The interrupt pending registers allow problems to be identified immediately by interrupt when they occur such as during an isolated power loss or when a cable is broken due to someone tripping on the cable or breaking it off with a ladder. These interrupts may be individually disabled by clearing the IPENLA-- register bits.

OCETV - Occurrence, Error, Timing Violation, Falling edge triggered signal input.

This status register is read/write. The register is set by a timing violation, caused by not having enough time to load the FIFOs before the end of the next cycle. This is very unlikely to occur, because the FIFOs are loaded with 16 channels of scaler data and 2 timestamps in under 1 mS, and the scalers are double buffered. If the next gate sampling time starts before the previous start of gate timestamp is written, then data and/or the timestamp are lost. The state machine that loads the FIFOs will require 1 mS to transfer (1) 32-bit start of gate timestamp and (16) 24-bit scaler counts plus status and (1) gate count and (1) 32-bit end of gate timestamp in this order. It should be noted that the scalers are double buffered, meaning that you can start counting again on the next gate without affecting the previous output, allowing overlap with the state machine load cycle. The error bit is used to flag the user that the start of gate timestamp will not be correct as it has been overwritten prior to being loaded into the FIFOs. This interrupt may be disabled by clearing the IENTV register bit.

OCEG1 - Occurrence, Error, Glitch on DS1 VME-bus input. Rising edge triggered signal input.

This status register is read/write. This register is set whenever a second falling edge is detected on DS1 during three consecutive strobe samplings at 100 MHz. DS1 is guaranteed by VME-bus specification not to glitch, but if it does in a heavily loaded chassis, it will cause data errors so this condition will be monitored and will be flagged. This interrupt may be disabled by clearing the IENG1 register bit.

OCEG0 - Occurrence, Error, Glitch on DS0 VME-bus input. Rising edge triggered signal input.

This status register is read/write. This register is set whenever a second falling edge is detected on DS0 during three consecutive strobe samplings at 100 MHz. DS0 is guaranteed by VME-bus specification not to glitch, but if it does in a heavily loaded chassis, it will cause data errors so this condition will be monitored and will be flagged. . This interrupt may be disabled by clearing the IENG0 register bit.

OCEGA - Occurrence, Error, Glitch on AS, VME-bus input. Rising edge triggered signal input.

This status register is read/write. This register is set whenever a second falling edge is detected on AS during three consecutive strobe samplings at 100 MHz. AS is guaranteed by VME-bus specification not to glitch, but if it does in a heavily loaded chassis, it can cause data errors so this condition will be monitored and will be flagged. . This interrupt may be disabled by clearing the IENGA register bit.

OCIFC - Occurrence, Information, FIFO Cleared with unread data. Falling edge triggered signal input.

This status register is read/write. This register is set whenever a front panel fiducial or reset event occurs when one or more of the FIFOs are not empty (have not yet been read to completion). This is not an error if the data was intentionally ignored, but can be an error if the host processor board was too slow in retrieving all scaler board data prior to the front panel fiducial or reset event in a real-time application. This interrupt may be disabled by clearing the IENFC register bit.

OCEFF - Occurrence, Error, FIFO Full. Falling edge triggered signal input.

This status register is read/write. This register is set whenever one or more of the FIFOs are full. This interrupt may be disabled by clearing the IENFF register bit.

OCIHF - Occurrence, Information, FIFO ½ full. Falling edge triggered signal input.

This status register is read/write. This register is set whenever one or more of the FIFOs are ½ full. This is a signal that the FIFO should be read soon to avoid overflow, it may indicate that the collection rate exceeds the read rate, or for slower applications as a stimulus for the host processor to collect data depending on the application. This interrupt may be disabled by clearing the IENHF register bit.

OCIDA - Occurrence, Information, FIFO Data Available. Rising edge triggered signal input.

This status register is read/write. This register is set whenever one or more of the FIFOs are not empty, (data is first available). This is a signal that the FIFO can now be read as data is available. This interrupt may be disabled by clearing the IENDA register bit. It is important to recognize that any data read from an empty FIFO is tri-stated and will appear as nearly random data from board to board.

OCIU3 - Occurrence, Information, Unaligned transfer (byte 1-3). Falling edge triggered signal input. This status register is read/write.

This register is set whenever an unaligned transfer (UAT) of byte 1-3 is done. This could be helpful in diagnosing VME-bus errors caused by violation of the bytewise ascending sequential order requirement. This interrupt may be disabled by clearing the IENU3 register bit.

OCIU2 - Occurrence, Information, Unaligned transfer (byte 1-2). Falling edge triggered signal input.

This status register is read/write. This register is set whenever an unaligned transfer (UAT) of byte 1-2 is done. This could be helpful in diagnosing VME-bus errors caused by violation of the bytewise ascending sequential order requirement. This interrupt may be disabled by clearing the IENU2 register bit.

OCIU1 - Occurrence, Information, Unaligned transfer (byte 0-2). Falling edge triggered signal input.

This status register is read/write. This register is set whenever an unaligned transfer (UAT) of byte 0-2 is done. This could be helpful in diagnosing VME-bus errors caused by violation of the bytewise ascending sequential order requirement. This interrupt may be disabled by clearing the IENU1 register bit.

OCIFE - Occurrence, Information, FIFO Empty. Falling edge triggered signal input.

This status register is read/write. This register is set whenever all of the FIFOs become empty. This information can be used to stop reading data, or to check that a reset has cleared the FIFOs. This interrupt may be disabled by clearing the IENFE register bit. It is important to recognize that any data read from an empty FIFO is tri-stated and will appear as nearly random data from board to board.

OCIT0 - Occurrence, Information, front panel fiducial or reset event input active. Falling edge triggered signal input.

This status register is read/write. This register is set whenever the front panel fiducial or reset event input is active. This interrupt may be disabled by clearing the IENT0 register bit.

OCIGT - Occurrence, Information, Gate input active. Falling edge triggered signal input.

This status register is read/write. This register is set whenever the Gate input is active. This interrupt may be disabled by clearing the IENGT register bit.

OCECO - Occurrence, Error, Counter Overflow. Falling edge triggered signal input.

This status register is read/write. This register is set whenever one or more of the scalers or timestamps overflow. A larger prescale setting may be necessary to prevent this occurrence. This interrupt may be disabled by clearing the IENCO register bit.

General note on Gate Count interrupts. We are watching for occurrences of bit transitions here on the gate counter. We cannot preset a count to trigger on. For example, after 3 gates, the OCIGCNT0&1 status are high, after 5 gates OCIGCNT0&1&2 are high, after 8 gates OCIGCNT0&1&2&3 are high etc. You may wish to interrupt on OCIGCNT3 when the counter reaches 8, OCIGCNT4 for 16, OCIGCNT5 for 32 etc. We may add some comparison logic and extra registers later if a specific gate count needs to be loaded and compared to trigger an interrupt, if Altera resources permit. Also note that the real-time gate count can be read directly or by polling RTGCNT0-7 anytime without using interrupts.

OCIGCNT0 - Gate Count, bit 0. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every odd gate count starting with 1 (i.e. 1,3,5, etc.). This interrupt may be disabled by clearing the IENGCNT0 register bit.

OCIGCNT1 - Gate Count, bit 1. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every fourth gate count starting with 2 (i.e. 2,6,10 etc.). This interrupt may be disabled by clearing the IENGCNT1 register bit.

OCIGCNT2 - Gate Count, bit 2. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every eighth gate count starting with 4 (i.e. 4,12,20 etc.). This interrupt may be disabled by clearing the IENGCNT2 register bit.

OCIGCNT3 - Gate Count, bit 3. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every sixteenth gate count starting with 8 (i.e. 8,24,40 etc.). This interrupt may be disabled by clearing the IENGCNT3 register bit.

OCIGCNT4 - Gate Count, bit 4. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every thirty-secondth gate count starting with 16 (i.e. 16,48,80 etc.). This interrupt may be disabled by clearing the IENGCNT4 register bit.

OCIGCNT5 - Gate Count, bit 5. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every sixty-fourth gate count starting with 32 (i.e. 32,96,160 etc.). This interrupt may be disabled by clearing the IENGCNT5 register bit.

OCIGCNT6 - Gate Count, bit 6. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every one hundred twenty-eighth gate count starting with 64 (i.e. 64,192,320 etc.). This interrupt may be disabled by clearing the IENGCNT6 register bit.

OCIGCNT7 - Gate Count, bit 7. Rising edge triggered signal input.

This status register is read/write. The gate counter is used to set a threshold for servicing data by the host computer. For each gate occurrence there are 18 32-bit quantities to read out of the FIFOs. This register is set every sixty-fourth gate count starting with 128 (i.e. 128,384,640 etc.). This interrupt may be disabled by clearing the IENGCNT7 register bit.

OCIBERR - Occurrence, Error, Buss Error. Falling edge triggered signal input.

This status register is read/write. This register is set whenever a VME-bus BERR* (bus error) occurs. This may happen as a result of trying to access the FIFO out of ascending bytewise sequential order or providing an incorrect (AM) address modifier code. A FIFO retransmit command may need to be executed to recover from this BERR*. This interrupt may be disabled by clearing the IENBERR register bit.

OCEUBLT - Occurrence, Error, Unaligned Block Transfer. Falling edge triggered signal input.

This status register is read/write. This register is set whenever an attempt is made to generate an unaligned block transfer. Only 32-bit BLTs are supported. This is unlikely to occur if VxWorks is controlling transfers. This interrupt may be disabled by clearing the IENUBLT register bit.

OCIBLT - Occurrence, Information, Block Transfer. Falling edge triggered signal input.

This status register is read/write. This register is set whenever a BLT occurs. It can be used for diagnostic purposes of VME-bus transfers. Only 32-bit BLTs are supported. This interrupt may be disabled by clearing the IENBLT register bit.

OCISBT - Occurrence, Information, Single Byte Transfer. Rising edge triggered signal input.

This status register is read/write. This register is set whenever a single byte transfer occurs. It can be used for diagnostic purposes of VME-bus transfers. All single byte transfer types are supported. Users are cautioned about the rules for the ascending bytewise sequential access FIFO interface. It is easier to keep track of bytes using 32-bit transfers! Any violations will cause a BERR*. This interrupt may be disabled by clearing the IENSBT register bit.

OCIDBT - Occurrence, Information, Double Byte Transfer. Rising edge triggered signal input.

This status register is read/write. This register is set whenever a double byte transfer occurs. It can be used for diagnostic purposes of VME-bus transfers. All VME-bus double byte transfer types are supported. Users are cautioned about the rules for the ascending bytewise sequential access FIFO interface. It is easier to keep track of bytes using 32-bit transfers! Any violations will cause a BERR*. This interrupt may be disabled by clearing the IENDBT register bit.

OCITBT - Occurrence, Information, Triple Byte Transfer. Rising edge triggered signal input.

This status register is read/write. This register is set whenever a triple byte transfer occurs. It can be used for diagnostic purposes of VME-bus transfers. All VME-bus triple byte transfer types are supported. Users are cautioned about the rules for the ascending bytewise sequential access FIFO interface. It is easier to keep track of bytes using 32-bit transfers! Any violations will cause a BERR*. This interrupt may be disabled by clearing the IENTBT register bit.

OCIQBT - Occurrence, Information, Quad Byte Transfer. Rising edge triggered signal input.

This status register is read/write. This register is set whenever a quad byte transfer occurs. It can be used for diagnostic purposes of VME-bus transfers. This interrupt may be disabled by clearing the IENQBT register bit.

OCEILL - Occurrence, Error, Illegal VME bus transfer code. Falling edge triggered signal input.

This status register is read/write. This register is set whenever an illegal code that is not supported by the VME-bus specification occurs. It can be used for diagnostic purposes of VME-bus transfers. This interrupt may be disabled by clearing the IENILL register bit.

STID0 - Command, set Status ID bit 0. User set Status ID output signal.

This command register is read/write. This register supplies bit 0 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

STID1 - Command, set Status ID bit 1. User set Status ID output signal.

This command register is read/write. This register supplies bit 1 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

STID2 - Command, set Status ID bit 2. User set Status ID output signal.

This command register is read/write. This register supplies bit 2 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

STID3 - Command, set Status ID bit 3. User set Status ID output signal.

This command register is read/write. This register supplies bit 3 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

STID4 - Command, set Status ID bit 4. User set Status ID output signal.

This command register is read/write. This register supplies bit 4 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

STID5 - Command, set Status ID bit 5. User set Status ID output signal.

This command register is read/write. This register supplies bit 5 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

STID6 - Command, set Status ID bit 6. User set Status ID output signal.

This status register is read/write. This register supplies bit 6 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

STID7 - Command, set Status ID bit 7. User set Status ID output signal.

This command register is read/write. This register supplies bit 7 in the status ID for the VME-bus on-board interrupter. It can be set to uniquely identify what board is interrupting, or provide user set status to the host computer servicing the interrupt.

IRQL0 - Command, Interrupt Reque