D09-E2440 FANOUT UNIT

last revision October 11, 1995

1.0 FANOUT UNIT
1.1 Introduction
1.2 Fanout Unit Characteristics
1.3 Jumper patch options
2.0 Theory of Operation
2.1 Timeline Inputs
2.2 Timeline Carrier/Data Regeneration
2.3 PLD188 U4 Data Buffer and Timeline Carrier Indicator
3.0 D09-E2442 Fanout Assembly Test
3.1 D09-E2442 Fanout Assembly
3.2 Hazards
3.3 Initial tests
3.4 Program/verify Programmable Integrated Circuit
3.4.1 Testing Suspect Programmable Integrated Circuit
3.5 AT&T T7032 Jumper Patching
3.6 Initial power application
3.7 Initial Printed Wiring Board Assembly Tests
3.8 Timeline LED Driver Tests - LEDs not installed
3.9 Fiber Optic Printed Wiring Board Assembly Tests
3.9.1 AT&T Bypass Tests With Wire Input
3.9.2 AT&T Bypass Tests With Fiber Optic Input
3.10 Front Panel Assembly Tests

1.0 FANOUT UNIT

1.1 Introduction

The event codes are transmitted using a serial modified Manchester code (bi-phase-mark). Bi-phase-mark guarantees a signal level transition at each cell edge, rather than the center as is done in the true Manchester code (bi-phase). A binary "one" is defined as a level transition in the cell center, while no transition is a binary "zero". The timeline transmission rate is 10M bi-phase-mark cells/sec.

Normally, the D09-E2442 front panel assembly (fanout unit) does not contain a data recovery circuit. In cases where the timeline signal is distorted, a AT&T 7032 clock/data recovery circuit can be installed. The clock/data recovery circuit accommodates transmission rates between 7.5M and 12.2M bi-phase-mark cells/sec by changing the clock recovery integrated circuit center frequency patch.

The timeline event code encoder transmits a continuous stream of binary ones while idle. Therefore, the timeline idle condition is a 10 MHz 50% duty cycle square wave carrier.

Event codes are transmitted asynchronous in time, however event codes are synchronized to the timeline carrier when transmitted. An event code transmission consists of 12 bi-phase cells:

1. 1-START cell (always a binary zero)
2. 8-DATA cells (data transmitted MSB first)
3. 1-PARITY cell (even parity - including the START bit)
4. 2-STOP cells (always binary one's)

Therefore, 1.2 usec are required to transmit an event code, and the maximum event code transmission rate is 833,333 codes/second.

The primary function of the PARITY cell is to restore the phase of the timeline idle ones (it also provides a data check). During normal operation, the phase of the idle ones between event codes is mark-space: positive-negative referenced to the standard copper wiring. If standard phase idle ones are transmitted, the event code start bit phase is mark (positive) phase.

The timeline convention for twin-axial wire cable connections is male pin to transmitter or receiver non-inverted output or input (female pin to inverted output or input). The receiver is isolated from the transmitter by transformer coupling the receiver input. The timeline twin-axial cable transmission is point-to-point, not party line, therefore multiple timeline users must obtain timeline signals from timeline fanout assemblies.

NOTE: The Fanout Unit was designed with a direct fiber optic input option. However, between design and production, AT&T dropped the fiber optic receiver integrated circuit from their product line. Thus, the direct fiber optic line input has been deleted. However, printed wiring for the circuit exists, therefore the bypass jumper must be installed.

1.2 Fanout Unit Characteristics

• Input:
• Copper wire: Differential TTL transmission on shielded twisted pair copper wire.
• Transformer coupled to the differential receiver IC.
• Connector Amphenol 31-2225 twin-axial BNC (BNL A-69622).
• Mating connector Amphenol 31-2226 (BNL A-69809)
• Cable: Beldon 9463 is replacing the RG108A cable (BNL A-30350).
• Input signal conditioning option:
• AT&T T7032 clock recovery circuit. Center frequency adjustable from 7.5 to 12.2 MHz
• Outputs:
• 16 buffered differential TTL timeline outputs.
• Connectors Amphenol 31-2225 twin-axial BNC (BNL A-69622).
• Mating connectors Amphenol 31-2226 (BNL A-69809)
• Cable: Beldon 9463 is replacing the RG108A cable (BNL A-30350).
• Indicators:
• - RED LED indicating power on.
• - GREEN LED indicating timeline carrier detected.

1.3 Jumper patch options

2.0 Theory of Operation

Reference drawings:
     D09-E2436 Schematic Diagram - Fanout Assembly 
  f.o. D09-E2438 Printed Wiring Board Assembly - Fiber Optic Fanout Assembly
       D09-E2439 Front Panel Drill & Screening - Fanout Assembly
  f.o. D09-E2440 Front Panel Assembly - Fiber Optic Fanout Assembly
  wire D09-E2441 Printed Wiring Board Assembly - Fanout Assembly
  wire D09-E2442 Front Panel Assembly - Fanout Assembly
       PLD188 PAL Design Listing (CUPL format)

2.1 Timeline Inputs

NOTE: Transformer U10 secondary center tap may be AC terminated to ground. If used, the center tap will stabilize at 1/2 Vcc due to a resistive divider within U2.

The fiber optic cable input is received by U1, an AT&T RX1352E multimode fiber optic receiver with an ST connector. The fiber optic cable may be either single mode or multi mode. U1 converts the received optical signal into a differential TTL output. U1 STATUS U1-13, is connected to MUTE U1-14. If the fiber optic input signal is lost, STATUS will MUTE (disable) the differential TTL output. The differential TTL output of U1 is converted to a single ended TTL output in U2.

NOTE: The AT&T recommended power filter circuit on pin 4 (VA). The circuit provides a filtered Vcc to the fiber optic receiver amplifiers.

NOTE: The AT&T RX1352 fiber optic receiver was discontinued in the Fall of 1994. No D09-E2440 were fabricated.

2.2 Timeline Carrier/Data Regeneration

The AT&T T7032 clock recovery circuit U3 retimed data output can be bypassed via jumper patch J23. Jumper J23, BYPASS is input to PLD188 U4. BYPASS switches the buffered data output (U4-18 & U4-17) source between the RAW[1..0] inputs, and the retimed U3 input. The retimed data is buffered in U4, and converted to differential TTL outputs in 26LS31 TTL differential driver ICs U5, U6, U7, and U8. The recovered clock output is input to PAL U4.

NOTE: Table 1.2, nominal center values, are half those shown the AT&T T7032 data sheet due to the timeline bi-phase-mark transmission. For other timeline frequencies patch the AT&T T7032 clock recovery IC U3 center frequency per table 1.2.

The AT&T T7032 clock recovery circuit time base is a simple NTSC television color burst crystal CR1 (3.579545 MHz). The AT&T T7032 clock recovery circuit has a data descrambler circuit which is used in telecommunications applications to eliminate the transmission of long strings of NRZ-L binary ones or zeros. The timeline bi-phase-mark transmission technique does not allow long strings binary ones or zeros in an NRZ-L format. Therefore, patch J19 is normally installed to disable the descrambler.

2.3 PLD188 U4 Data Buffer and Timeline Carrier Indicator

The two raw timeline outputs of the differential receiver 26LS32 U1, are input to the PLD188 along with the AT&T T7032 data output. Jumper patch J18, SELECT, and J23, BYPASS, are also input. The five signals are combined and output (pins 16..19) as follows:

OUTPUT = !BYPASS & TIMELINE
        # BYPASS & (RAW0 & !SELECT # RAW1 & SELECT);

The same expression is output on pin 14. The output is looped back into PLD188 through a capacitor. The input is biased to +5V through a small resistor, and DC restored in diode D1. If the selected timeline carrier is present, the carrier will be buffered by PAL188 LED output. The carrier will drive the GREEN carrier LED on. The feedback circuit is used as a timeline input failure could force the selected input into a steady mark condition.

2.4 LED Displays

The power RED LED DS2 is driven by fanout module the power supply output through current limiting resistor R11.2.0 ASSEMBLY AND TEST PROCEDURES

3.0 D09-E2442 Fanout Assembly Test

3.1 D09-E2442 Fanout Assembly

Reference drawings: 
       D09-E2436 Schematic Diagram - Fanout Assembly 
  f.o. D09-E2438 Printed Wiring Board Assembly - Fiber Optic Fanout
Assembly 
       D09-E2439 Front Panel Drill & Screening - Fanout Assembly
  f.o. D09-E2440 Front Panel Assembly - Fiber Optic Fanout Assembly
  wire D09-E2441 Printed Wiring Board Assembly - Fanout Assembly
  wire D09-E2442 Front Panel Assembly - Fanout Assembly
PLD188 PAL Design Listing (CUPL format)

NOTE: Drawings marked f.o. have not been revised to A level.

3.2 Hazards

3.3 Initial tests

1. With no integrated circuits installed, test for a short between the GROUND (E40) and +5V (E39) planes.
2. Using the printed wiring board assembly drawing D09-E2441 install the integrated circuits.
3. With the components installed, test for a short between the GROUND (E40) and +5V (E39) planes.
4. With the all components installed, using drawing D09-E2436, test for continuity between the GROUND pin (E40), and integrated circuit ground pins: U2-8, U3-16, U4-12, U5-8, U6-9, U7-8, U9-8.
5. With the all components installed, using drawing D09-E2436, test for continuity between the POWER pin (E39), and integrated circuit power pins: U2-16, U3-19, U4-24, U5-16, U6-16, U7-16, U9-16.

3.4 Program/verify Programmable Integrated Circuit

U4, PLD188, 22V10

1. PROM listing found in PLD188 file.
2. Program with the Stag 3000 Universal Programmer equipped with a Zm 3000 personality module.
3. Following programming, label the programmed part using the device name PLD188, date, and checksum.

3.4.1 Testing Suspect Programmable Integrated Circuit

1. U4, PLD188, 22V10 listing found in PLD188 file.
2. Equip the Stag 3000 Universal Programmer with a Zm 3000 personality module.
3. Read and verify the PROM against PLD188 listing and the checksum at the time it was programmed.

3.5 AT&T T7032 Jumper Patching

Using jumper links, such as Vero part number 188-39180G, patch the assembly in the following locations:

1. J23 BYPASS: jumper on - use AT&T circuit
2. J18 LSEL: jumper on - wire input
3. J19 DSCR: jumper on - AT&T data descrambler disabled
4. J20, J21, J22 Center frequency - ON, OFF, OFF (10 MHz for test)

NOTE: Jumper order on printed wiring board is J23, J18, J19, J20, J21, J22 (left to right).

3.6 Initial power application

1. Obtain a 5V, 5A power supply with current limiting.
2. Set the power supply to 5.0VDC, current limit to 2 ADC.
3. Connect the power supply to GROUND (E40) and +5V (E39).
4. Apply primary power to the power supply, and turn on DC voltage using preset current limit.
5. Check the current drawn by the printed wiring board assembly. The assembly should be no more than 0.7 ADC. If the power supply current limits - immediately turn off the primary power, and check for shorts or reverse insertion of integrated circuits.
6. Check the integrated circuits for excessive heating (excessive means: cannot hold finger on circuit while operating), indicating (DIP) reverse insertion in the module.

3.7 Initial Printed Wiring Board Assembly Tests

1. Obtain D09-E2530 Fanout Assembly Test Box, and a short twin-axial cable assembly with Amphenol 31-2226 connectors on both ends (note 1). In one end insert an Amphenol 31-2225 bulkhead connector. Connect the other end to the D09-E2530 Fanout Assembly Test Box output connector. If a D09-E2530 Fanout Assembly Test Box is not available, use one of the operating timelines.
2. Obtain an oscilloscope (minimum: analog dual trace oscilloscope with 100 MHz bandwidth).
3. Insert timeline source cable bulkhead connector terminal female and male pins into E-points 1 and 2 (input J1) respectively. The bulkhead connector will stay in place without solder.
4. Apply primary power to the power supply, and turn on DC voltage using preset current limit.
5. Connect the oscilloscope ground to the timeline cable shield, and probe one to J1 male connector pin (E2). Synchronize to the positive going edge of the signal. Set to view a few cycles of the 10 MHz square wave (note 2).
6. With probe two, examine: Transformer U10 output pin 1, in phase; and output pin 3 out of phase with the probe one reference. Reduced amplitudes (note 2 & 3).
7. With probe two, examine: Differential receiver U2 output 3, in phase with the probe one reference but displaced in time approximately 20 ns. TTL amplitude, the signal should look "cleaner" than the timeline input (note 2).
8. Move the oscilloscope ground to the printed wiring board assembly ground, and probe one to differential receiver output U2-3. Synchronize to the positive going edge of the signal. Set to view a few cycles of the 10 MHz square wave.
9. With probe two, examine: AT&T clock recovery circuit data output U3-9, in phase with the probe one reference. The TTL amplitude signal should be a "perfect" representation of the timeline input, but displaced in time.
10. With probe two, examine: AT&T clock recovery clock output U3-10, the clock rising edge should be in phase with the rising and falling edges of the probe one reference. TTL amplitude signal should be a "perfect" 20 MHz square wave synchronous to the timeline input, but displaced in time.
11. With the oscilloscope grounded to the printed wiring board assembly ground, and probe one connected to the AT&T clock recovery data output U3-9. Synchronize to the positive going edge of the signal. Set to view a few cycles of the 10 MHz square wave.
12. With probe two, examine: PLD188 (22V10) outputs U4-17, U4-18, U4-19, and U4-20. The outputs should be in phase with the probe one reference, TTL amplitude, and the signal should be a duplicate of the restored data output, but displaced in time.
13. With probe two, examine: Differential driver U5, U6, U7, and U8 outputs 2, 6, 10, and 14. The outputs should be in phase with the probe one reference. TTL amplitude, the signal should be a duplicate of the restored data output, but displaced in time.
14. With probe two, examine: Differential driver U5, U6, U7, and U8 outputs 3, 5, 11, and 13. The outputs should be out of phase with the probe one reference. TTL amplitude, the signal should be a duplicate of the restored data output, but displaced in time.

NOTE: 1. Check the timeline cable shield connection to the twin-axial connector outside shell. If the connector outside shell rotates freely on either end; the shield is not connected to the outside shell - discard the cable, and obtain a cable with its shield connected to the twin-axial connectors. Also test the cable twin-axial pins wiring; male to male, and female to female. If incorrectly connected discard the cable.

NOTE: 2. In all the test procedures, if an active timeline is used, the 10 MHz square wave display will include background event code transmissions.

NOTE: 3. If transformer U10 center tap AC ground is installed, the signals will be symmetrical about 2.5 VDC.

NOTE: 4. Transformer U10 appears to be a 6-pin DIP, however the "dot" in the transformer case identifies pin 6 - not pin 1. For assembly only, the "dot" is considered pin 1.

NOTE: 5. The timeline signal is delayed approximately 100 ns between the input connector J1, and the output connectors J[2..17]. A delay of approximately 20 ns occurs in each circuit; U2, U4, and U[5..8]. With the largest delay occurring in the AT&T clock recovery circuit U3.

3.8 Timeline LED Driver Tests - LEDs not installed

1. Use probe 1 to measure E35, and E36 potentials. E35 should be ground and E36 should be +5V is no LED is installed.
2. With a timeline input, the timeline LED indicator driver can be tested. With the oscilloscope grounded to the printed wiring board assembly ground, connect probe one to either PAL188 timeline output J14. Synchronize to display a few cycles of the timeline carrier.
3. With probe two examine: PLD188 input U4-7. It should a DC restored version of the signal on probe one.
4. With probe two, examine: PLD188 LED driver output U4-15 (E-37). The LED drive will be the same as probe one, but displaced in time.
5. c. Disconnect the timeline input (J1). With the oscilloscope trigger AUTO, the PLD188 LED driver output U4-15 (E-37) will be a steady TTL one level.

3.9 Fiber Optic Printed Wiring Board Assembly Tests

If the final assembly is a fiber optic assembly D09-E2440:

1. Install U1, an AT&T RX1352E fiber optic receiver.
2. Remove jumper link J18, check the assembly jumper locations:
3. J18 LSEL: jumper off - fiber optic input
4. J19 DSCR: jumper on - AT&T data descrambler disabled
5. J20, J21, J22 Center frequency - ON, OFF, OFF (10 MHz for test)
6. J23 BYPASS: jumper on - use AT&T circuit
7. Remove the timeline input J1 if installed.
8. Remove the plastic cover from the fiber optic input to U1. Store the plastic cover for later use. Connect a fiber optic timeline cable to U1.
9. Connect probe 1 to differential receiver U2-13 to check for the presence of timeline. Synchronize to the positive going edge of the signal. Set to view a few cycles of the 10 MHz square wave.
10. With probe two, examine: AT&T clock recovery circuit data output U3-9, in phase with the probe one reference. This checks the data selector in the clock recovery circuit.
11. With probe two, examine: PLD188 (22V10) outputs U4-17, U4-18, U4-19, and U4-20. The outputs should be in phase with the probe one reference. This checks the PLD188 data selector.
12. With probe two, examine: Differential driver U5, U6, U7, and U8 outputs were tested in step 2.6.g.

3.9.1 AT&T Bypass Tests With Wire Input

1. Remove AT&T clock recovery circuit U3.
2. Change the jumper locations:
3. J18 LSEL: jumper on - wire input
4. J19, J20, J21, J22: remove, not utilized
5. J23 BYPASS: jumper off - bypass AT&T circuit
6. Set the timeline source, cables, and oscilloscope per 2.6 a - e.
7. Connect probe 1 to differential receiver U2-3 to check for the presence of timeline. Synchronize to the positive going edge of the signal. Set to view a few cycles of the 10 MHz square wave.
8. With probe two, examine: 1. PLD188 (22V10) outputs U4-17, U4-18, U4-19, and U4-20. The outputs should be in phase with the probe one reference. This checks the PLD188 data selector.
9. With probe two, examine: 2. Differential driver U5, U6, U7, and U8 outputs were tested in step 2.6.g.

3.9.2 AT&T Bypass Tests With Fiber Optic Input

1. Remove AT&T clock recovery circuit U3.
2. J18 LSEL: jumper off - fiber optic input
3. J19, J20, J21, J22: remove, not utilized
4. J23 BYPASS: jumper off - bypass AT&T circuit
5. Attach fiber optic timeline source to input U1.
6. Connect probe 1 to differential receiver U2-13 to check for the presence of timeline. Synchronize to the positive going edge of the signal. Set to view a few cycles of the 10 MHz square wave.
7. With probe two, examine: PLD188 (22V10) outputs U4-17 and U4-18. The outputs should be in phase with the probe one reference. This checks the PLD188 data selector.
8. With probe two, examine: Differential driver U5, U6, U7, and U8 outputs were tested in step 2.6.g.

3.10 Front Panel Assembly Tests

1. Obtain a D09-E2439 front panel, and assemble as a fiber optic version, D09-E2440, or wire version, D09-E2442. Install connectors J[1-17], and LEDs DS[1..2].
2. NOTE: LED DS[1..2] orientation, LED flat side to odd numbered E-points.
3. Attach printed wiring board assembly D09-E2438 (fiber optic) or D09-E2441 (wire) to the front panel by soldering J[1-17]. Next, solder LEDs DS[1..2].
4. Attach chassis bottom of chassis assembly D09-M-770-4 to front panel. Attach power supply to chassis bottom. Connect power supply to printed wiring board.
5. Run power cord though chassis top of chassis assembly D09-M-770-4 assess hole with bushing installed. Connect the primary power cable to the power supply.
6. Obtain the Pomona Box differential to single-ended cable converter and two short lengths of cable. One twin-axial cable assembly with Amphenol 31-2226 connectors on both ends, and the other a coaxial cable with BNC connectors on both ends.
7. Connect primary power. The +5V DC LED should illuminate red. If not remove primary power and recheck the final assembly.
8. Connect a timeline to J1 input for wire and U1 for fiber optic. The TIMELINE carrier LED should indicate green as the carrier is detected.
9. Connect the Pomona Box differential to single-ended cable converter BNC cable end to an oscilloscope input. Do not use the oscilloscope 50 termination, use the 1M input. Connect the twin-axial connector to J2 through J17 and test for a normal TTL level output.

Name          PLD188;
Partno        PLD188;
Revision      C;
Device        P22V10;
Date          October 19, 1994;
Designer      C. R. Conkling Jr;
Company       Brookhaven National Laboratory;
Location      U4;
Assembly      D09-E2441;
/******************************************************/
/*  Fanout Unit                                       */
/*  Revision For final PCB layout D09-E2437-5 Rev A   */
/******************************************************/
/** pins **/
Pin 1 = NC1;
Pin 2 = !RAW0; /*twin-axial differential timeline - raw data */
Pin 3 = RAW1; /*AT&T fiber optic - raw data*/
Pin 4 = SELECT; /*select fiber optic input to AT&T chip*/
Pin 5 = !TIMELINE; /*AT&T clock recovery chip - recovered data*/
Pin 6 = BYPASS; /*bypass AT&T clock recovery chip*/
Pin 7 = CARRIER_IN; /*LED driver input*/
Pin 8 = NC8;
Pin 9 = NC9;
Pin 10 =NC10; 
Pin 11 =NC11;
Pin 23 = NC23;
Pin 22 = MC22;
Pin 21 = NC21;
Pin 20 = OUTPUT0; /*buffered timeline*/
Pin 19 = OUTPUT1; /*buffered timeline*/
Pin 18 = OUTPUT2; /*buffered timeline*/
Pin 17 = OUTPUT3; /*buffered timeline*/
Pin 16 = NC16;
Pin 15 = LED; /*LED indicator driver*/
Pin 14 = OUTPUT4; /*buffered timeline*/
Pin 13 = NC13;
LED = CARRIER_IN;
/*inversion of inputs RAW0 and TIMELINE compensates U2 input
connection*/
OUTPUT0 = (!BYPASS & TIMELINE 
         #  BYPASS & (RAW0 & !SELECT # RAW1 & SELECT));
OUTPUT1 = (!BYPASS & TIMELINE 
         #  BYPASS & (RAW0 & !SELECT # RAW1 & SELECT));
OUTPUT2 = (!BYPASS & TIMELINE 
         #  BYPASS & (RAW0 & !SELECT # RAW1 & SELECT));
OUTPUT3 = (!BYPASS & TIMELINE 
         #  BYPASS & (RAW0 & !SELECT # RAW1 & SELECT));
OUTPUT4 = (!BYPASS & TIMELINE 
         #  BYPASS & (RAW0 & !SELECT # RAW1 & SELECT));