RHIC UTILITY MODULE (V108) FUNCTIONAL DESCRIPTION

AND MEMORY MAP

PAUL STEIN

Rev 1.3

26 Oct 99

The RHIC utility module shall be a multi-purpose board used to provide the front end computer (FEC) residing in a VME chassis with interfaces to certain RHIC communication links, input/output capability and chassis environment information. The utility module shall be designed to reside in a VME chassis, shall occupy one VME board slot (4HP front panel width) and fit into a 6U X 160mm standard Eurocard form factor. The front panel of the utility module will contain connectors for input signals and LED's to indicate certain status conditions. Additional inputs shall be provided on a 6U X 80mm transition module if needed. The five front panel input signals, event link, RTDL, remote reset and external interrupts A & B have P2 connections so that they can be brought into the utility module via a transition module if desired. The utility module shall require +5V, +/-12V power. The utility module shall communicate with the FEC over the VME back plane. The utility module's VME interface shall be a buss slave type and support A24 and D16 and D8(O). The interrupter sections shall be I(x) interrupters, D08(O) and respond with an 8 bit status/id on D00- D07. The interrupters on the utility module will clear interrupt requests using the Release On Register Access (RORA) method.

The main features of the utility module are as follows:

RHIC event link (timeline) decoder and timeline filter used to generate VME interrupts.

RHIC real time data link (RTDL) receiver and data frame buffer.

RTDL link error monitor.

Event link (timeline) error monitor.

Link status indication for Timeline, RTDL, Remote reset and board initialization.

Power supply, fan and temperature monitoring for the VME chassis.

Interrupt generation from failed links, power supplies, fans and over temperature.

Remote reset of VME chassis capability.(List of V108 Reset Addresses)

VME interrupts from two external signal sources.

Board ID Prom (displays VMEid Message)

A. VME base address of the utility module - The utility module will respond to A24 type addressing and will respond to address modifier code of 3D, standard supervisory data access (24 bit address) and 39, standard non-privileged data access (24 bit address). The base address of the utility module will be set using VME address bits A23-A14. For the purpose of giving the addresses of various registers and memory locations on the utility module, this document will assume that the base address will be 0xf0004000 since this is the base address that V108's will be configured to.

B.RHIC EVENT LINK decoder section - This portion of the utility module is responsible for receiving RHIC timeline events and generating VME interrupts for those events specified by the FEC. This section will contain a timeline receiver, filter lookup RAM and priority FIFO's. There are 256 unique event codes on the RHIC timeline. For each event there will be an associated entry in the filter RAM. Each entry will consist of 2 bits. The 2 bits of each entry are control bits for the filter and are called the interrupt enable control bit and the priority control bit. The interrupt enable control bit will be used to specify if the corresponding timeline event will be used to generate an interrupt or not. There are two interrupt levels on the utility module specified for RHIC timeline events, high priority and low priority. If an event is specified to generate an interrupt, the priority control bit will specify if it is a low priority or high priority event. There is one vector register for all timeline events. The timeline int. status register read during the RORA int. ack. cycle will provide a read back of the timeline event that generated the interrupt. The following table summarizes the action of the two control bits.

PRIORITY INTERRUPT ENABLE

CTRL BIT CTRL BIT ACTION

=================================================================

X | 0 | event does not generate interrupt

X | 0 | event does not generate interrupt

0 | 1 | event generates low priority int.

1 | 1 | event generates high priority int.

NOTE: X means don't care condition

TABLE 1.

When the utility module receives a timeline event, its 8-bit code is used to address the filter RAM. If the interrupt enable bit is a 0 (zero) then no further action is taken. If the interrupt enable bit is a 1 (one) and the priority bit is a 0 (zero) and there are no other low priority or any high priority events pending then an interrupt will be generated immediately. If there are other events pending, then the event code queued in the low priority FIFO. When a low priority event is at the head of the queue it will generate a VME interrupt providing there are no high priority events waiting in the high priority FIFO. It is important to note that a low priority event can only generate a VME interrupt when the high priority FIFO is completely empty.

If the interrupt enable bit is a 1 (one) and the priority bit is a 1 (one) and there are no other high priority events pending then a VME interrupt will be generated immediately. If there are other high priority events pending, then the event code will be placed in the high priority FIFO until it becomes the head of the queue. If there are any low priority events pending, they will be preceded by the high priority event.

The high and low priority FIFO's shall each be 16 entries deep. If a FIFO is completely full any new events to that FIFO are ignored and thus will be lost. A status byte indicating that a FIFO is full and events have been lost will be included. This status will be latched in a register readable by the FEC over the VME buss. When read by the FEC, the status latch will be cleared.

NOTE: Caution should be used in the number of events used to generate interrupts for fast cycling machines such as the AGS or Booster. The FIFOs should be empty by the end of a machine cycle. If a FIFO is not empty, then an event from a previous cycle will cause an interrupt in the next cycle.

The utility module will pull on only one VME interrupt line for all timeline events. The choice of high priority/low priority event is strictly internal to the utility module. However since there are 7 VME interrupt lines, the utility module will provide a routing circuit that will allow the FEC under software control, to specify which one of the 7 VME interrupt lines to use for timeline event interrupts. The following table summarizes the routing circuit control.

ROUTING CONTROL BITS

B2 B1 B0 ACTION

=======================================

0 0 0 | disable VME interrupt

0 0 1 | route to VME int. level 1

0 1 0 | route to VME int. level 2

0 1 1 | route to VME int. level 3

1 0 0 | route to VME int. level 4

1 0 1 | route to VME int. level 5

1 1 0 | route to VME int. level 6

1 1 1 | route to VME int. level 7

TABLE 2.

It will be the responsibility of the FEC to write the vector, the filter control bits and the routing control bits. Thus these will be available as writable/readable registers on the VME buss. The status/id returned during an interrupt service will be the vector written into the timeline int vector register and thus will also be available on the VME buss.

The following registers and memory locations are used for timeline interrupt control and monitoring.

Timeline interrupt vector register - VME address 0xf0004065: This register contains the 8-bit status/id vector returned during a timeline interrupt cycle. This register also supports standard VME D8(o) reads and writes.

Timeline interrupt routing register - VME address 0xf0004041: This register contains the VME interrupt level (1-7) for the timeline interrupt. Supports standard VME D8(o) reads and writes. This register is 8 bits wide with the following format, XXXXXb2b1b0, where X means don't care and b2, b1 and b0 are set as shown in Table 2 above. Note this register is reset to zero upon a VME system reset.

Timeline status register - VME address 0xf000405d: This register contains the hex code of the timeline event generating an interrupt and is read as a standard VME D8(o) read cycle by the interrupt handler routine. When this register is read, it will clear the interrupt request (RORA). This register is one byte wide.

FIFO status - VME address 0xf0004055: This register reads back different status conditions for the high and low priority fifo's. For each FIFO there are three conditions, full error, full and empty. Full error indicates that a write was attempted to a FIFO that was already full. Full indicates that the maximum number of entries has been reached and empty indicates there are no entries in the FIFO. Full error status is active high, full and empty statuses are active low. This register is 8 bits wide and uses the following format, 00EhFhElFlFelFeh, where:

Eh = empty status for high priority FIFO

Fh = full status for high priority FIFO

El = empty status for low priority FIFO

Fl = full status for low priority FIFO

Fel = full error status for low priority FIFO

Feh = full error status for high priority FIFO

After this register is read, only the full error status bits are cleared. This register supports VME D8(o) reads only.

FIFO reset - VME address 0xf000406d: A read of this register is used to clear the FIFO's. This is important during initialization of the board. No valid information is returned when this register is read. Supports VME D8(o) reads only.

Timeline parity errors - VME address 0xf0005851: This register is a readback of timeline parity errors. The readback is a 2 digit hexadecimal number. Errors are counted using an 8 bit binary counter. The range of values is 00 - 255 decimal. The register is 8 bits wide and supports VME D8(o) reads only.

Timeline frame errors - VME address 0xf000584d: This register is a readback of timeline frame errors. The readback is a 2 digit hexadecimal number. Errors are counted using an 8 bit binary counter. The range of values is 00 - 255 decimal. The register is 8 bits wide and supports VME D8(o) reads only.

Filter control - VME addresses 0xf0004801 - 0xf00049ff inclusive and odd addresses only: There are 256 of these locations, one for each timeline event. Each location uses the lower two bits for the interrupt control using the following format 000000PI, where I is the interrupt enable control bit and P is the priority control bit. Please refer to Table 1 above. This table shows how these bits are set. To calculate which location corresponds to a particular timeline event use the following formula: (event code in hex X 2) + 4801h. For example to find out the location for event 0Ah, (0Ah X 2) + 4801h = 4815h, thus the location for this event is 0xf0004815. Each filter control location is 8 bits wide and supports VME D8(o) reads and writes.

The following steps must be taken to insure proper initialization of the timeline interrupt control at power up since the filter RAM will power up in a random state. This random state will cause false interrupts to occur if not properly initialized.

1 - clear all filter control locations by writing 00h to each location, (0xf0004801-0xf00049ff)

2 - clear the interrupt level by writing 00h to the timeline interrupt routing register (0xf0004041)

3 - reset the fifo's by reading the fifo reset location (0xf000406d)

4 - clear any pending interrupts by reading the timeline status register (0xf000405d)

The timeline interrupt control is now initialized. To start interrupts do the following:

1 - write the desired timeline interrupt vector to the vector register (0xf0004065)

2 - write the desired interrupt level to the routing register (0xf0004041)

3 - write the filter control bits to the desired filter locations.

C.RHIC Real Time Data Link (RTDL) Receiver section - This section of the utility board will be responsible for receiving RTDL frames, storing them and making them available to the FEC. This section of the utility board consists of a RTDL receiver and a RAM frame buffer. The frame buffer will be 24 bits wide since each machine parameter consists of 24 bits of data. There are 256 different machine parameters and each will have it's own entry in the buffer RAM. When a RTDL frame is received, its 8-bit parameter id will be used as the address into the frame buffer RAM to write the data. RTDL frames are transmitted at every tick of the 720Hz clock.

The RTDL frames start at location 0xf0006000. Each frame occupies 4 bytes of memory but since each frame consists of 24 data bits, only the lower 3 bytes carry any meaningful information. There are 256 - 4 byte locations, one for each possible RTDL parameter id. Thus the range of addresses for all 256 frames is 0xf0006000 - 0xf00063fc in 4 byte chunks. The 4 bytes are arranged in standard VME format with byte 0 being the MSB and byte 3 the LSB. For the RTDL frames byte 0 is undeclared, byte 1 contains the upper 8 bits of the 24 bit frame, byte 2 contains the middle 8 bits of the 24 and byte 3 contains the lower 8 bits. Each frame can be read by the FEC as either 4 8-bit bytes or as 2 16-bit words. When read as 16-bit words, the upper word contains bytes 0-1 and the lower word bytes 2-3. To calculate the base address of any RTDL frame use the following formula: (RTDL frame parameter id in hex X 4) + 6000h. For example if we wanted to access the RTDL frame whose parameter id is 10 (0Ah), then plugging into the formula yields (0Ah X 4) + 6000h = 6028h, thus the base address for this frame is 0xf0006028. Byte 1 is located at base + 1 (0xf0006029), byte 2 at base + 2 (0xf000602a) and byte 3 at base + 3 (0xf000602b).

As a diagnostic for checking RTDL function on a V108, the C0h parameter id frame can be used. This frame starts at location 0xf0006300h in the RTDL memory and updates every 4 - 5 seconds. The actual value is a running count.

RTDL frames can be read and written by the FEC, however writing is a special case that is only to be used to initialize the RTDL frame buffers to 000000h. To do this simply write the word 0000h to byte 2 & 3 of each frame. It is important that only word access and data 0000h is used otherwise proper initialization will not occur. It is also important to note that using the RTDL frame buffer area as a regular scratchpad RAM area will not work. VME byte write access and/or writing data besides 0000h will result in unexpected and erroneous data. VME write access to RTDL frame buffers shall only be used to initialize frame to 000000h.

Since RTDL frames are written 24 bits at a time and read from VME as 2 16-bit words, the possibility for incorrect data exists. This can happen for example if the upper word of a frame is read from VME, then the frame is updated from the RTDL receiver before VME can read the lower word. In this case the upper word read contains old data, while the lower frame read contains new data. Thus the whole frame is inconsistent and should be considered wrong. To solve this problem multiple reads of a frame are necessary. The frame should be repeatedly read until two consecutive reads contain the same value. This should take no more then 4 consecutive reads of any RTDL frame.

D. RTDL link error status - Parity errors and frame errors from RTDL transmissions will be recorded and available to the FEC. Each error type will have it's own 8 bit binary counter. The count value will indicate the number of detected errors. The RTDL receiver outputs a parity error signal when it detects bad parity in a received frame and a frame error signal when it detects the wrong polarity of the frame stop bit. These errors can occur independent of each other.

RTDL parity errors - VME address 0xf0004051: This register is the read back for the RTDL parity errors. The read back is interpreted as a 2 digit hexadecimal number. Errors are counted using an 8 bit binary counter. The range of values is 00 - 255 decimal. This register is 8 bits wide and supports VME D8(o) reads only.

RTDL frame errors - VME address 0xf000404d: This register is the read back for the RTDL frame errors. The read back is interpreted as a 2 digit hexadecimal number. Errors are counted using an 8 bit binary counter. The range of values is 00 - 255 decimal. This register is 8 bits wide and supports VME D8(o) reads only.

E. Power supply, fan, temperature and links monitor (Environment Monitor) - This section of the utility module will monitor the +5V, +12V, -12V VME chassis DC power supplies, the five chassis cooling fans (Note: the five status signals for the fans are wired OR'ed and thus only one status bit is brought to the utility module), the chassis temperature and the timeline, RTDL and remote reset links. Together these comprise an environment monitor. If any of these is found not to be working properly, the utility module will assert a VME interrupt. Note only one interrupt per fault per condition will be generated. If a fault remains active, the utility module will not continuously generate interrupts for that fault. The fault must first go inactive before another interrupt is generated. Also each fault condition will be monitored independently thus each can independently assert an interrupt. Status registers will be provided on the utility module that the FEC can read and will contain the information on exactly what has failed. The following registers are used to control the environment monitor.

Note: The microcontroller that monitors the environmental input status bits will not generate an interrupt until the environment vector register has been initialized. This will enable the proper handling of faults that might occur before the board has been initialized. This can occur for instance if the RTDL link was disconnected while the chassis is being turned on.

Environment interrupt vector register - VME address 0xf0004049: This register contains the 8-bit status/id returned during an environment interrupt cycle. This register also supports standard VME D8(o) reads and writes.

Environment interrupt routing register - VME address 0xf0004045: This register contains the VME interrupt level (1-7) for the environment interrupt. Supports standard VME D8(o) writes only. This register is 8 bits wide with the following format, XXXXXb2b1b0, where X means don't care and b2, b1 and b0 are set as shown in the table below. Note this register is reset to zero upon a VME system reset.

The following table summarizes the routing circuit control for the environment interrupt.

ROUTING CONTROL BITS

B2 B1 B0 ACTION

=======================================

0 0 0 | disable VME interrupt

0 0 1 | route to VME int. level 1

0 1 0 | route to VME int. level 2

0 1 1 | route to VME int. level 3

1 0 0 | route to VME int. level 4

1 0 1 | route to VME int. level 5

1 1 0 | route to VME int. level 6

1 1 1 | route to VME int. level 7

TABLE 3

Environment interrupt routing read back register - VME address 0xf0004041: This register is the read back for the environment interrupt level routing. This register supports VME D8(o) reads and has the following format Xb2b1b0XXXX where X is don't care and b2, b1 and b0 are as shown in the table 3 above.

Environment status register - VME address 0xf0004069: This register contains the status bits for the power supplies and the cooling fans and is read as a standard VME D8(o) read cycle by the interrupt handler routine. When this register is read, it will clear the interrupt request (RORA). This register is 8 bits wide and has the following format: b7b6b5b4XXXX, where X is don't care and the other bits have the following meaning:

b7 = +5V status

b6 = -12V status

b5 = +12V status

b4 = fan status

Each status bit indicates it's respective fault condition with a logic 1 and normal operation (no fault) with a logic 0.

Link status register - VME address 0xf0004059: This register contains the status bit for the temperature high read back and status bits for the various links. This register is 8 bits wide and supports standard VME D8(o) reads. It has the following format: XXb5b4b3b2b1b0, where X means don't care and the rest of the bits have the following meaning:

b5 = remote reset routing bit, 1 means remote reset drives VME sysrst, 0 reset drives P2 connector pin.

b4 = temperature high status, indicates over temperature fault has occurred.

b3 = board initialization bit

b2 = remote reset link status

b1 = timeline event link status

b0 = RTDL link status

The initialization bit will indicate that the software has initialized the board. This bit is cleared by a VME system reset and will read logic '0' when the board has been reset and not yet initialized. The bit will be set to a logic '1' when the timeline fifo reset register (0xf000406d) is read.

The temperature high status/link status is part of the environment monitor system that can generate VME interrupts. Thus this register must also be read as part of the environment interrupt handler, however reading this register does not clear an interrupt request. To properly acknowledge an environmental interrupt both the link status and the environment status register must be read as part of the interrupt handler.

The temperature high status bit reads logic 1 when an over temperature fault has occurred. The link status bits read logic 1 when a carrier signal is detected on each respective link and thus a logic 1 read back indicates normal operation for that link. A read back of logic 0 indicates no carrier has been detected and thus the link is not operational.

The over temperature threshold will be preset for 55 deg. C since most of the semiconductor components used on various boards have an operating temperature limit of 70 deg. C. The temperature threshold however can be changed.

Temperature read back register - VME address 0xf0004061: This register contains the actual temperature read back from the temperature sensor. It is 8 bits wide and supports standard VME D8(o) reads. To convert the reading to Celsius simply divide the reading by two. For example using a read back of 3Ch, in decimal this is 60. 60/2 = 30, thus the temperature is 30 deg. C.

To initialize the environment interrupt control after power up do the following steps:

1 - Write 0h to the environment routing register (0xf0004045)

2 - Read the environment status register (0xf0004069). This clears interrupt requests.

Now to start valid interrupt generation upon an environmental fault do the following:

1- Write the desired interrupt vector to the vector register (0xf0004049)

2 - Write the desired interrupt level to the routing register (0xf0004045)

F. Remote Reset Link Receiver - An independent communication link providing remote reset capability for each VME chassis will be used for RHIC. The receiver for this link will be located on the utility module. Each VME chassis in the system will have it's own unique remote reset address. The reset signal generated by the remote reset receiver will be jumper selectable to drive either the VME /sysrst line or pin A8 of the P2 connector. The jumper configuration selected is readable via the link status register (0xf0004059). Each remote reset address will be 16 bits in length. When the remote reset circuit receives an address transmission, it will compare the received address to the chassis' address. If the two are the same, the receiver will activate the VME system reset line (pin C12 of the P1 connector) for approximately 225 mSec or pin P2A 8. Note pin P2A8 contains it's own pull up resistor. A remote reset address transmission will consist of two separate frames, one containing the MSB of the 16-bit address and the other containing the LSB. In order to provide sufficient protection against erroneous chassis resets, the two frames must be received consecutively and within a specified time of each other. There is no FEC support needed for the remote reset link other then to read the link status register (0xf0004059) to see if the remote reset link is active and where it is routed to.

(V108 Remote Reset Address jumper Warning)

A valid remote reset address consists of the following:

MSB 1XXXXXXX

LSB 0XXXXXXX

(List of V108 Reset Addresses)

It is crucial to proper operation of the remote reset link that a synchronization code proceeds any valid remote reset address transmission. A synchronization code consists of the following:

MSB 0XXXXXXX

LSB 1XXXXXXX

This code will synchronize the bi-phase mark receivers on the remote reset link and it will not cause any chassis' to reset since it does not represent any valid remote reset address.

The V103 RHIC Master Reset Module is the VME board that transmits the remote reset addresses to V108s via the Remote Reset Link.

G. Board ID Prom - The board ID prom will be readable by the FEC over the VME buss. It will contain the following information:

Board type (i.e. this board is a utility module)

Board serial number

Version number

Remote reset address

The address range for the ID prom is 0xf0004000 - 0xf000403f. Each information byte will support standard D8(o) VME reads. The even locations of the ID prom will be programmed with 2Eh. The 2Eh locations will support standard D8(e) VME reads.

H. VME interrupts from external sources - The capability of generating a VME interrupt from two external signal sources will be provided. Two optically isolated, 50 ohm-terminated inputs will provide the connection into the utility module for two external signal sources. The connector types used for the external interrupt inputs are LEMO connectors. There is one vector register for both external interrupt sources. An external interrupt status register is read during the RORA int. ack. cycle and will provide a read back of which channel generated the interrupt. The frequency of the signal source generating external interrupt requests is limited by the response time of the FEC. Until the current interrupt is cleared during RORA, any new interrupt requests are ignored.

The following registers are used for external interrupt control.

External interrupt vector register - VME address 0xf0005865: This register contains the 8-bit status/id vector returned during an external interrupt cycle. This register also supports standard VME D8(o) reads and writes.

External interrupt routing register - VME address 0xf0005841: This register contains the VME interrupt level (1-7) for the external interrupts. Supports standard VME D8(o) reads and writes. This register is 8 bits wide with the following format, XXXXXb2b1b0, where X means don't care and b2, b1 and b0 are as shown in Table 4 below. Note this register is reset to zero upon a VME system reset.

ROUTING CONTROL BITS

B2 B1 B0 ACTION

=======================================

0 0 0 | disable VME interrupt

0 0 1 | route to VME int. level 1

0 1 0 | route to VME int. level 2

0 1 1 | route to VME int. level 3

1 0 0 | route to VME int. level 4

1 0 1 | route to VME int. level 5

1 1 0 | route to VME int. level 6

1 1 1 | route to VME int. level 7

TABLE 4.

External interrupt status register - VME address 0xf000585d: This register contains status bits that indicate which external interrupt channel generated the interrupt request. This register is read as a standard VME D8(o) read cycle by the interrupt handler routine. When this register is read, it will clear the interrupt request (RORA). This register is 8 bits wide with the following format, XXXXXXCbCa, where X means don't care and Cb is the status bit for external interrupt channel B and Ca is the status bit for external interrupt channel A. A one (1) indicates the channel is generating an interrupt request.

To turn on external interrupts do the following:

1. - write the desired vector to the external interrupt vector register (0xf0005865)

2. - write the desired interrupt level to the external int. routing register (0xf0005841)

To turn off external interrupts do the following:

1. - write 00h to the external interrupt routing register (0xf0005841)

I. The following table shows all the memory locations described in the document above.

DESCRIPTION VME ADDR_______________________________VME ADDR RANGE

==========================================================================

ID PROM___________________________________________0xf0004000 - 0xf000403f

TIMELINE INT ROUTING/ ENV. INT ROUTING READBACK___0xf0004041

ENVIROMENT INT ROUTING____________________________0xf0004045

ENVIROMENT INT VECTOR_____________________________0xf0004049

RTDL FRAME ERRORS_________________________________0xf000404d

RTDL PARITY ERRORS________________________________0xf0004051

TIMELINE FIFO STATUS______________________________0xf0004055

LINK STATUS_______________________________________0xf0004059

TIMELINE CODE STATUS______________________________0xf000405d

TEMPERATURE READBACK REGISTER_____________________0xf0004061

TIMELINE INT VECTOR_______________________________0xf0004065

ENVIROMENT STATUS_________________________________0xf0004069

TIMELINE FIFO RESET_______________________________0xf000406d

TIMELINE FILTER CONTROL RAM_______________________0xf0004801 - 0xf00049ff

EXTERNAL INT ROUTING______________________________0xf0005841

TIMELINE FRAME ERRORS_____________________________0xf000584d

TIMELINE PARITY ERRORS____________________________0xf0005851

EXTERNAL INT STATUS_______________________________0xf000585d

EXTERNAL INT VECTOR_______________________________0xf0005865

RTDL FRAME BUFFER RAM_____________________________0xf0006000 - 0xf00063fc

Displaying the ID prom from a typical utility board will provide you with the following information:

*.V.M.E.I.D.B.N.L* - This board manufactured by BNL

*.V.1.0.8........* - Board type, V108 is the utility board identifier

*...C.....0.1.7.2* - Rev C, serial number 172

*...F.5.3.A......* - Remote Reset Address for SN 172 is F53A

For a Rev A, V108 Utility Module the following P1 backplane jumper configuration is required for the slot that the board will be in:

Installed

[ ] BG0

[ ] BG1

[ ] BG2

[ ] BG3

Removed

[ ] IACK

For a Rev B and Rev C, V108 Utility Module the following P1 backplane jumper configuration is required for the slot that the board will be in:

Removed

[ ] BG0

[ ] BG1

[ ] BG2

[ ] BG3

[ ] IACK

A three pin connector for the fan fail sensor is factory wired to the P2 connector of slot 2, thus the utility board should be placed in this slot. However the connector could be moved to slot 3 if needed. If the sensor connector is moved to slot 3, the following connections must be made:

Blue wire to P2A5

Black wire to P2A6

To have the remote reset signal drive the VME /SYSRST line (P1C12) the following jumper configuration must be used:

[ ] 58 - 60

[ ] 59 - 61

To have the remote reset signal drive P2A8 (user defined) the following jumper configuration must be used:

[ ] 62 - 60

[ ] 63 - 61

 WARNING: The remote reset address jumpers (E25 - E50, inclusive) are preconfigured and tested by the RHIC controls group. The user MUST NOT change the configuration of these jumpers.

NOTE: The remote reset address jumpers for each V108 are configured to a predetermined and unique reset address and do not require any action by the user. The jumpers for the reset address are E25 - E50, inclusive.

VME SEL - LED, lights when a V108 is being accessed from VME.

UC1 - LED, indicates that the temperature sensor microcontroler is running. This LED blinks at a 5-7 sec rep. rate.

UC2 - LED, indicates that the environment interrupt microcontroller is running and monitoring the environment inputs (i.e. fans, voltages) for fault conditions. NOTE this LED will not light until the software has properly initialized the V108 board.

EVENTLNK - LED and TWIN-AX connector, The TWIN-AX is used for Event Link input to the V108. The LED will light when an active EVENT LINK carrier is detected by the V108. The LED will be off when there is no active carrier.

RSTLNK - LED and TWIN-AX connector, The TWIN-AX is used for Remote Reset Link input to the V108. The LED will light when an active Remote Reset Link carrier is detected by the V108. The LED will be off when there is no active carrier.

RTDL - LED and TWIN-AX connector, The TWIN-AX is used for RTDL input to the V108. The LED will light when an active RTDL carrier is detected by the V108. The LED will be off when there is no active carrier.

EXINTA - LEMO connector, Input for an external interrupt signal source for external interrupt channel A. This input is optically isolated.

EXINTB - LEMO connector, Input for an external interrupt signal source for external interrupt channel B. This input is optically isolated.

The following P2 pins duplicate front panel connections:

The V108 is preconfigured for a base address of 0xf0004000.

To configure the V108 for a base address of 0xf0004000 the following jumpers are needed:

[ ] E2 - E14

[ ] E3 - E15

[ ] E4 - E16

[ ] E5 - E17

[ ] E6 - E18

[ ] E7 - E19

[ ] E8 - E20

[ ] E9 - E21

[ ] E10 - E22

[ ] E11 - E24

[ ] E57 - E23

[ ] SW1 - OPEN

[ ] SW2 - CLOSED

[ ] SW3 - OPEN

[ ] SW4 - OPEN

The most up to date revision level (as of this documents revision date) for a V108 board is REV C.

Rev C - ECN AG00197 - Changed U18 and U19 to 74LS645-1 and U43 to 74LS641-1.

Rev B - ECN AG00187 - Added connections to board for jumping across bus grant signals /BG0, /BG1, /BG2 and /BG3.

Rev A - original design.

Altera PLD Revision History -

94028111, CtrlStat, U2 Rev 1.3/Rev A, original design

94028109, IntrFace, U1 Rev 1.8/Rev A, original design

94028113, RmRstChp, U28 Rev 0.9/Rev A, original design

94028110, RTDLChip, U3 Rev 0.2/Rev A, orignal design

94028112, VintChip, U41 Rev 0.5/Rev A, ECN CAD0006

94028114, TimeRecv, U8 Rev 0.2/Rev A, original design

MicroChip PIC Revision History-

94028116, UtilTemp, U9 Rev 0.5/Rev A, original design

94028115, IntCtl, U29 Rev 0.3/Rev A, original design