Functional Overview

V124 Beam Sync Trigger Module

H. Hartmann

April 3,1998

Revised 5/11/98

Revised 6/8/98

 

1.0 Introduction *

2.0 Theory of Operation and Triggering Modes *

2.1 Theory of Operation *

2.2 Triggering Modes *

3.0 Configuration parameters *

3.1 Board Configuration *

3.1.1 Bucket One Position Counter *

3.1.2 VME Interrupt configuration *

3.2 Channel Configuration *

3.2.1 Command/Status Register *

3.2.2 Revolution Counter Enable Selector *

3.2.3 Bucket Counter Enable Selector *

3.2.4 Trigger Counter Clock Selector *

3.2.5 Pulse Width Counter Enable Selector *

3.2.6 Fine Counter Clock Selector *

3.2.7 Timestamp Trigger (latch) Selector *

3.2.8 Time Stamp Clock Source *

3.2.9 Rearm on Trigger Counter Terminal Count (Halt Trigger) *

3.3 On Board Memory *

4.0 System Status parameters *

4.1 Board Status *

4.1.1 Interrupt/Error Status *

4.2 Channel Status *

4.2.1 Status Flags *

4.2.2 Revolution Counter *

4.2.3 Bucket Counter *

4.2.4 Trigger Counter *

4.2.5 Pulse Width Counter *

4.2.6 Fine Counter *

4.2.7 Timestamp Counter *

5.0 Front Panel Connectors and Indicators *

5.1 Front Panel Connectors *

5.1.1 Twin Axial *

5.1.2 LEMO *

5.2 Front Panel Indicators *

6.0 Limitations *

  

1.0 Introduction

The Beam Sync Trigger Module (V124) is a general-purpose 6U x 4HP, VMEbus controlled module that is compatible with the RHIC Beam Synchronous Event System and is designed to provide clocks and triggers for collider data acquisition systems and experiments. The RHIC Beam Synchronous Event Link consists of centralized event encoders (one each for the blue and yellow rings), which operate from the RF clock and the revolution clock provided by the RHIC RF system.

There are 360 RF buckets (buckets) per ring. Only a fraction of these will contain beam (bunches). The V124 Module contains a separate 360 bit memory (Bunch Fill Mask RAM) for each channel that is software configurable with the pattern of filled buckets (Bunch Fill Pattern) to permit flexible triggering/clocking. This module provides eight identical channels that can be configured independently or in pairs, and a buffered RF Clock output.

2.0 Theory of Operation and Triggering Modes

2.1 Theory of Operation

Beam Synchronous Event codes will be used by the Event Mask RAM to determine if a particular event is being used for triggering. Events selected for triggering will be synchronized to the revolution clock before triggering a channel. The Beam Synchronous Clock will be extracted from the input data stream so that the RF Clock (2x Beam Synchronous Clock) can be recovered. Recovery will be accomplished by phase locking to the Beam Synchronous Event Link carrier and boosting the frequency by a factor of 2. Recovery of the RF Clock is mandatory for triggering on certain bunch fill patterns. (RHIC/AP-132)

The Revolution Clock Event (bsx-revtick) is transmitted when bucket #1 passes the RF wall current monitor located in the 4 o’clock sector. Transmission delays of events are equalized such that each event is received at all locations at the same time. The RF Clock will always be used for clocking the Bucket 1 Position Counter. The Revolution Clock is delayed by the Bucket 1 Position Counter and yields the Delayed Revolution Clock. The Bucket 1 Position Counter synchronizes the occurrence of the Revolution Clock Event with the occurrence of Bucket 1 passing by the particular hardware location. This allows the Bunch Fill Mask RAM to always reference the Bunch Fill Pattern to Bucket #1.

Eight identical trigger channels are resident on each module. Each channel consists of four programmable, cascadable counters: revolution, bucket, trigger and fine. The revolution counter is enabled by the revolution counter enable selector which is user selectable. After the revolution counter is enabled, counting of the revolution clock will start with its next occurrence. This allows delaying to a particular revolution. The bucket counter can be enabled by the revolution counter reaching terminal count. Once enabled, the bucket counter counts RF clocks until terminal count is reached. This allows delaying to a particular bucket within a specified revolution. After the bucket counter has reached terminal count, it enables the trigger counter which can count the RF buckets identified by the trigger pattern loaded into the Bunch Fill Mask RAM. The Fine Counter is enabled on the occurrence of the bucket counter enable and disabled on the occurrence of the trigger counter terminal count. The Fine Counter allows phase adjustment within a specified bucket. These delays will support the triggering modes as described in Section 2.2.

Each channel can be configured with a unique bunch fill pattern. The pattern is loaded into the Bunch Fill Mask RAM and the contents are shifted out a bit at a time at the RF Clock rate. Each bit corresponds to an RF bucket and determines whether that bucket will be used for triggering. The shifting is synchronized to the delayed revolution clock such that the sequence starts over at each occurrence of the delayed revolution clock.

Each channel provides a Timestamp to allow data correlation between data acquisition equipment and experiments of different systems. The Timestamp counter is configured to count either Beam Synchronous Events or 1m s clocks derived from the Rhic Event Link and is reset on the occurrence of a RHIC Beam Synchronous Event Link SYNC Event. The timestamp register is configured to save the contents of the timestamp counter on the occurrence of a Beam Synchronous Event (software configurable), a trigger pulse or trigger counter terminal count. The timestamp register must be read before another timestamp save occurs or the contents will be overwritten.

2.2 Triggering Modes

This module supports the following triggering modes:

  1. One or more pulses output every revolution, pulse width selectable, triggered after x number of revolution clocks. Rearm on Trigger Counter Terminal Count (Halt Trigger).
  2. One or more pulses output after x number of turns and y number of bunches. Rearm on Trigger Counter Terminal Count (Halt Trigger). (See timing diagrams #1 and #2)
  3. One or more pulses output after specified event and y number of bunches. Rearm on Trigger Counter Terminal Count (Halt Trigger).
  4. Long Gate. Start is defined by channel 1 and Trigger Counter Terminal Count (Halt Trigger) is defined by channel 2.
  5. One pulse output continuous for each bunch in bunch fill pattern not to exceed 9.37MHz. Pulse width is 54ns. No Trigger Counter Terminal Count (Halt Trigger). (See timing diagram #3)
  6. All above modes can be configured as one-shot mode. (No rearm on Trigger Counter Terminal Count (Halt Trigger)).

3.0 Configuration parameters

3.1 Board Configuration

The following configuration parameters are programmable for the trigger module. These parameters are common to all channels.

All counters are configured as a counter and a hold register. The hold register is transferred to the counter when the register is written over the VMEbus, and when the appropriate terminal count has been reached along with the Rearm and Reload counters on channel Trigger Counter Terminal Count (Halt Trigger) command.

3.1.1 Bucket One Position Counter

A single 16-bit register will be provided to delay the Revolution Clock to account for different locations around the ring. The delay will be programmable from 1 to 512 (9 bits) to allow a delay to any bucket. The clock input to this counter is the recovered RF clock. The contents of the hold register is transferred to the counter on the occurrence of the Bucket 1 Position Counter Terminal Count.

 

3.1.2 VME Interrupt configuration

The trigger module generates a single VME Interrupt. The VME Interrupt level and interrupt vector are programmable via on-board registers. Any one of the following conditions can generate the interrupt:

  1. Time stamp trigger source.
  2. Sync Event
  3. Event Link Carrier error
  4. Event Link Frame error
  5. Event Link Parity error
  6. Beam Sync Link Carrier error
  7. Beam Sync Link Frame error
  8. Beam Sync Link Parity error
  9. Channel Trigger Counter Terminal Count (Halt Trigger)

3.2 Channel Configuration

Eight identical delay channels are provided. Each channel is configured with the following information:

3.2.1 Command/Status Register

 An eight-bit register will be provided to send commands to individual channels and to monitor counter statuses.

The following counter commands will be provided:

Rearm and Reload counters on channel Trigger Counter Terminal Count (Halt Trigger)

VMEbus Trigger

VMEbus Reset

STOP

REARM

The following counter statuses will be provided:

Waiting for Revolution Counter Terminal Count(Revolution count in progress)

Waiting for Bucket Counter Terminal Count (Bucket count in progress)

Waiting for Trigger Counter Terminal Count (Trigger count in progress)

 

3.2.2 Revolution Counter Enable Selector

Revolution Counter Enable Selector is selectable to be one of the following:

 

  1. VMEbus. A write to the VMEbus Trigger bit in conjunction with this selection will cause immediate triggering.
  2. An Event. This is a decoded Beam Sync Event.
  3. External. A front panel connector will be provided for external trigger input.
  4. Previous Channel Fine Counter Enable. (Not Channel 1.)

 

3.2.3 Bucket Counter Enable Selector

 

Bucket Counter Enable Selector is programmable to be one of the following:

 

  1. VMEbus. A write to the VMEbus Trigger bit in conjunction with this selection will cause immediate triggering.
  2. An Event. This is a decoded Beam Sync Event.
  3. Revolution Counter Terminal Count .

 

3.2.4 Trigger Counter Clock Selector

 

Trigger Counter Clock Selector is programmable to be one of the following:

 

  1. Fine Counter Clock.
  2. Next Channel Bucket Counter Terminal Count.
  3. No clock.

 

3.2.5 Pulse Width Counter Enable Selector

The Pulse Width Counter Enable Selector is programmable to be one of the following:

 

  1. Channel Bunch Fill Pattern
  2. Bucket Counter Terminal Count

 

3.2.6 Fine Counter Clock Selector

The Fine Counter Clock Selector is programmable to be one of the following:

  1. Fixed Pulse Width. One or more pulses derived from the Bunch fill pattern and the 28MHz RF clock with each pulse having a width of 54ns. In this case, the setting of the Pulse Width Counter Enable Selector is irrelevant.
  2. Variable Pulse Width. This is a single pulse or series of pulses with programmable width derived from the Pulse Width Counter Enable Selector.

 

3.2.7 Timestamp Trigger (latch) Selector

The Timestamp Trigger Selector is programmable to be one of the following:

  1. A Beam Sync Event (including the revolution event)
  2. First Pulse Trigger (of a series)
  3. Trigger Counter Terminal Count (Halt Trigger)

 

3.2.8 Time Stamp Clock Source

The Time Stamp Clock source is selectable to be one of the following

  1. The 1m s clock derived from the RHIC Event Link carrier.
  2. Beam Synchronous event

3.2.9 Rearm on Trigger Counter Terminal Count (Halt Trigger)

Each channel may be configured to rearm all triggers and reload all counters on the occurrence of a trigger counter terminal count (Halt Trigger) for that channel.

 3.3 On Board Memory

 VMEbus ID Prom (64 bytes), Board Configuration registers (16 bytes), Channel Configuration registers (256 bytes), Beam Sync Event Mask RAM (256 bytes), and Bunch Fill Mask RAM (384 bytes) are mapped to VMEbus A16 space on jumper selectable 1K byte boundary.

 4.0 System Status parameters

The following system configuration parameters are provided. These parameters are common to all 8-trigger channels. The associated hardware registers are listed for each parameter.

4.1 Board Status

 

4.1.1 Interrupt/Error Status

When the VMEbus interrupt occurs, the interrupt handler reads the interrupt status register to determine the cause of the interrupt. The error status register may be read outside the interrupt handler to determine the current status of the interrupt bits.

4.2 Channel Status

4.2.1 Status Flags

Individual bits in this parameter are used as status flags. The following status conditions are available:

 WAITING_FOR_REV_COUNTER

This bit indicates that Revolution Counter has been enabled but has not reached terminal count.

WAITING_FOR_BUCKET_COUNTER

This bit indicates that the Bucket Counter Enable has occurred but the Bucket Counter has not reached terminal count.

WAITING_FOR_TRIGGER

This bit indicates that the Trigger Counter has not reached terminal count.

HALT

This bit indicates that a trigger counter terminal count has occurred and the channel has not been rearmed.

RESET

This bit indicates that the channel is being held reset.

 4.2.2 Revolution Counter

The Revolution Counter is a 16-bit count-down counter that is preloaded with the revolution number and whose clock input is the Revolution Clock. This counter can be programmed with a count from 1 (12us) to 65536 (786ms). This counter is enabled from the output of the Revolution Enable Selector. The contents of the hold register is transferred to the counter on the occurrence of the Trigger Counter Terminal Count (Reload). The following two values can be read via the VMEbus:

a. Preloaded Count Value. This is the 16-bit value that is loaded into the Revolution Counter.

b.Current Count Value. This is lsByte value of the Revolution Counter. It is read on the fly and consecutive reads may yield different values. This value is used for diagnostic purposes.

4.2.3 Bucket Counter

The Bucket Counter is a 16-bit loadable/ 10 bit used count-down counter that is preloaded with the bucket number and whose clock input is the phase locked RF Clock. This counter can be programmed with a count from 1 to 1024 to allow a delay of least two full revolutions. Caution should be used when loading a value of more than 360, as this will cause a delay of greater than one revolution. This register is enabled from the output of the Bucket Counter Enable Selector. The contents of the hold register is transferred to the counter on the occurrence of the Bucket Counter Terminal Count (Reload). The following two values can be read via the VMEbus:

 

a. Preloaded Count Value. This is the 16(10)-bit value that is loaded into the Bucket Counter.

b.Current Count Value. This is the lsByte value of the Bucket Counter. It is read on the fly and consecutive reads may yield different values. This value is used for diagnostic purposes.

4.2.4 Trigger Counter

The Trigger Counter is a 32-bit count-down counter that is preloaded with the trigger number and whose clock input is the output of the Trigger Counter Clock Selector. This counter counts the number of trigger outputs and can be set to any value from 1 to 4.29E9. The contents of the hold register is transferred to the counter on the occurrence of the Trigger Counter Terminal Count (Relaod). The following two values can be read via the VMEbus:

a. Preloaded Count Value. This is the 32-bit value that is loaded into the Trigger Counter.

b.Current Count Value. This is the lsByte value of the Trigger Counter. It is read on the fly and consecutive reads may yield different values. This value is used for diagnostic purposes.

4.2.5 Pulse Width Counter

The Pulse Width Counter is a 16-bit count-down counter that is preloaded with pulse width value and is enabled by the Pulse Width Enable Selector. This counter counts the phase locked RF clock input. The following value can be read via the VMEbus:

Preloaded Count Value. This is the 16-bit value that is loaded into the Pulse Width Counter and will determine the pulse width of the output pulse(s). The width can be set from 35ns (1) to 2.29ms (65536).

 

4.2.6 Fine Counter

This is the 8bit value (x2) that is loaded into each of the fine counter modules. Resolution is 500ps. The delay is adjustable from 20ns (latency) to 275ns. (Input pulse width specifications need to be followed to realize the maximum delay.)

 

4.2.7 Timestamp Counter

The Timestamp Counter is the 32-bit count-up counter that is reset on the occurrence of a Beam Synchronous Event Link SYNC Event. The value that is read is the most recent Timestamp Value. The Timestamp Counter can be configured to count Beam Synchronous Events or 1m s clocks derived from the Rhic Event Link.

5.0 Front Panel Connectors and Indicators

5.1 Front Panel Connectors

 

5.1.1 Twin Axial

The following inputs shall be provided via front panel twin axial connections:

Beam Synchronous Event Link (1)

Event Link (1)

  5.1.2 LEMO

The following shall be provided via front panel 2-conductor LEMO Model EGG Series 0B connectors:

External Trigger Inputs (4)

Trigger Outputs (8)

RF Clock (buffered) Output

The Trigger Inputs, Trigger outputs and RF Clock output are differential ECL levels.

5.2 Front Panel Indicators

VME Select – indicates a VME bus access to an address within memory space.

Beam Synchronous Event Link – Carrier Active

Event Link – Carrier Active

Trigger Active (8)

6.0 Limitations

This module cannot be configured to output a clock from one of the output channels at the RF clock rate. However, provision has been made to supply both the buffered RF clock and a programmable gate so that specific triggering needs can be achieved at the user hardware.

Due to the configuration of the Bunch Fill Mask RAM, when a user wants to reconfigure this RAM, some "down" time will be experienced while a new Bunch Fill Table is loaded to a particular channel.