FUNCTION OVERVIEW
V125 ABORT KICKER LOGIC MODULE
NIELS SCHUMBURG
MARCH 10, 1999
The RHIC abort kicker logic will be located in the 10 O’clock service
building. The kicker logic module will monitor the beam permit carrier and, if
the permit carrier is interrupted, will initiate a beam abort cycle. Two systems
are required per ring, so that if one fails there will always be a working backup.
The RHIC ring permit master, when attempting to establish the beam
permit, initiates a carrier of sufficient duration to allow it to propagate around
the accelerator and return to the master. During this time, the master "listens" on
its input for the carrier to return. If the carrier returns, beam permit is established.
If there is any system failure the carrier is interrupted. The abort kicker logic will
be logically positioned just before the permit system master module and will require
the presence of the permit carrier for at least 1 second before arming the kicker
logic. This will lessen the likelihood of issuing false kicker firing triggers.
The abort kicker logic module will require the absence of the permit
carrier for, typically, ten cycles (1 usec.) before the beam abort cycle is initiated. The
design will support a "jumpered" option of 8 to 16 cycles. Loss of permit is
asynchronous to beam revolution, therefore requiring a synchronous reference and
a fixed delay to position the beam gap at the abort kicker. To accomplish this, the
kicker logic waits for the revolution fiducial on the Beam Sync Link. The actual
location of the gap will depend on several factors as well as the propagation delay of
the fiducial to the 10 O’clock location. However, once the fiducial is received, there
will be a fixed, known delay until the gap is positioned at the abort kickers. The
maximum delay necessary to positioning the beam gap at 10 O’clock, after sensing
the fiducial, is one revolution or approximately 12.8 usec. The kicker logic will have
a maximum programmable coarse delay (8-bits) of 18.2 usec. using the 14.07 MHz
Beam Sync clock (71 nsec.). A programmable fine delay (8-bits) of 137.5 nsec. will
locate the beam gap with a 0.5 nsec. resolution. The gap is approximately 1 usec. in
duration, enough time to allow the abort kickers to rise to operating level.
The kicker logic will monitor the Beam Sync Link for the presence of a
revolution fiducial. A timer is started to "wait" for the revolution fiducial. If it is not
detected within 2.5 beam revolutions (32 usecs.), and there is a loss of permit
carrier, a backup trigger will asynchronously initiate the abort firing sequence.
There may be times when it is desirable to dump the beam in one or both
rings in RHIC, such as at the end of the store, without dropping the beam permit.
The kicker logic module shall support a dump event to initiate a beam abort
sequence. A beam abort sequence initiated by detection of a Beam Dump event code,
shall follow the same synchronization and delay sequence as an abort initiated by
loss of permit carrier.
Associated with each beam abort will be a 32-bit time stamp. It will retain
its contents until read by the FEC. A parallel running counter will be synchronous
with the Reset code from the event link. A beam abort will transfer the
synchronous count to the time stamp register.
There are two status registers that will latch all information pertinent to
each beam abort. They will also indicate information on the quality of transmission
of the Beam Sync Link and the Event Link.
Events on the Beam Sync Link and the Event Link will be Manchester Bi-
Phase Mark Encoded with the following format:
1 start bit
8 bit event field
1 parity bit
2 stop bits
The permit carrier signal will be a constant 10 MHz clock signal when the
beam is running, any system failure will inhibit its transmission and initiate the
beam abort sequence.
Prior to the Beam Abort Fire Trigger a Stop Charge Trigger will be
transmitted to the kicker power supply logic. It will be coincident with the detection
of the revolution fiducial subsequent to an abort condition and will preceed the Abort
Trigger by one ring revolution (12.8 usec.) plus the programmable delays.
The VME power on or the reset sequence will initialize the system by
clearing all status register flags, all addressable registers, and the one second timer
which arms the kicker logic. The FEC has the responsibility to reestablish the
configuration parameters. If one of the two kicker logic boards is reset, just before
a beam abort sequence, the other takes charge. After the time stamp register is read,
on the controlling board, both boards will function in a redundant manner.
The following configuration parameters are programmable for the abort
kicker module .
A single 8-bit register will be provided to determine which Event Link code
to "look for" to initiate the beam abort sequence.
A single 8-bit register will be provided to select which Event Link code shall
reset the time stamp counter. This synchronizes the time stamp counter with the FEC
to obtain a precise beam abort time.
A single 8-bit register will be provided to determine which Beam Sync code
to "look for" to synchronize an abort condition with the beam.
A single 8-bit register will be provided to determine the fixed delay, after
locating the revolution fiducial, to position the beam gap by the kickers. The delay
will have a 71 nsec. resolution and a maximum value of 18.19 usec.
A single 8-bit register will provide for a vernier setting for the fixed delay.
It wii have a 0.5 nsec. resolution and a maximum value of 137.5 nsec. Because
the fine delay line has a step 0 delay of 10 nsec., it might be desireable to have the
coarse delay count have an offset of –1 to locate the beam gap more precisely.
The abort kicker module generates two VME interrupts. The VME interrupt
level and interrupt vector are programmable via on-board registers. Any one of the
following conditions can generate an interrupt:
Status Register1
Status Register2
revolution fiducial return
There are two status registers which will each provide for a single interrupt
enable bit. This is a programmable bit to enable or disable interrupts.
VME ID prom (64 bytes); programmable beam dump, reset, revolution
fiducial, coarse delay, fixed delay (5 bytes); two status, vector and routing
registers (6 bytes); and the time stamp (4 bytes). They are mapped to VME A16
space on a switch selectable 128 byte boundary.
When the VME interrupt occurs, the interrupt handler reads the interrupt
status register to determine the cause of the interrupt. The error status may be read
outside the interrupt handler to determine the current status of the interrupt bits.
Beam Dump
This flag indicates that the Beam Dump code was detected on the Event Link.
It is cleared when the time stamp is read and is used to identify the abort cause.
Real Time Beam Abort
This flag indicates when in time a beam abort has occurred. It "freezes" the
Beam Dump, Permit Failure, and Revolution Fiducial Failure flags until the time
stamp is read. At this time the flag is cleared.
Permit Failure
This flag indicates when a permit failure has occurred. It is cleared upon
detection of the permit carrier for at least one second.
Revolution Fiducial Failure
This flag indicates when it was not detected on the Beam Sync Link. When
the abort occurs this flag is "froozen", until the time stamp is read, so that it will
indicate whether the abort was synchronous or asynchronous (missing revolution
fiducial). It is updated once every beam revolution or every 12.8 usec.
This is a 32-bit value of the most recent beam abort time in usecs. Since last
Reset Event.
The following 3 inputs and 1 output shall be provided via front panel twin
axial connectors.
Beam Sync Link
Event Link
Permit Carrier In
Permit Carrier Out
The following outputs shall be provided via front panel coaxial (Lemo)
connectors:
Stop Charge
Beam Abort Fire Trigger
VME Select – Indicates a VME bus access to an address within
memory space
Beam Sync Link – Carrier active
Event Link – Carrier active
Permit Carrier – Carrier active